參數資料
型號: MT28F320A18
廠商: Micron Technology, Inc.
英文描述: FLASH MEMORY
中文描述: 閃存
文件頁數: 26/37頁
文件大?。?/td> 558K
代理商: MT28F320A18
2 MEG x 16
1.8V ENHANCED+ BOOT BLOCK FLASH MEMORY
PRELIMINARY
2 Meg x 16, 1.8V Enhanced+ Boot Block Flash Memory
MT28F320A18_3.fm - Rev. 3, Pub. 9/2002
2002, Micron Technology Inc.
26
READ CYCLE
Addresses can be accessed in a random order with
an access time given by
t
AA = 70ns.
When CE# and OE# are LOW, the data is placed on
the data bus and the processor can read the data.
STANDBY MODE
I
CC
supply current is reduced by applying a logic
HIGH level on CE# and RP# to enter the standby mode.
In the standby mode, the outputs are placed in High-Z.
Applying a CMOS logic HIGH level on CE# and RP#
reduces the current to I
CC2
(MAX). If the device is dese-
lected during an ERASE operation or during program-
ming, the device continues to draw current until the
operation is complete.
AUTOMATIC POWER SAVE MODE (APS)
Substantial power savings are realized during peri-
ods when the array is not being read and the device is
in the active mode. During this time, the device
switches to the automatic power saving mode. When
the device switches to this mode, I
CC
is reduced to
I
CC2
. The low level of power is maintained until
another operation is initiated. In this mode, the I/O
pins retain the data from the last memory address read
until a new address is initiated. This mode is entered
automatically if no address or control signal toggles.
POWER-UP SEQUENCE
The following power-up sequence is recommended
to properly initialize internal chip operations:
At power-up, RST# should be kept at V
IL
for 2μ
S
after V
CC
reaches V
CC
(MIN).
VccQ should not come up before Vcc.
V
PP
should be kept at V
IL
to maximize data integ-
rity.
When the power-up sequence is completed, RST#
should be brought to V
IH
. To ensure proper power-up,
the rise time of RST# (10%–90%) should be < 10μ
S
.
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