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參數(shù)資料
型號(hào)： MSC8103VT1200F
廠商： Freescale Semiconductor
文件頁數(shù)： 54/104頁
文件大?。?/td> 0K
描述： IC DSP 16BIT 300MHZ 332-FCPBGA
標(biāo)準(zhǔn)包裝： 90
系列： StarCore
類型： SC140 內(nèi)核
接口： 通信處理器模塊（CPM）
時(shí)鐘速率： 300MHz
非易失內(nèi)存： 外部
芯片上RAM： 512kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.60V
工作溫度： -40°C ~ 75°C
安裝類型： 表面貼裝
封裝/外殼： 332-BFBGA，F(xiàn)CPBGA
供應(yīng)商設(shè)備封裝： 332-FCBGA（17x17）
包裝： 托盤
AC Timings
MSC8103 Network Digital Signal Processor, Rev. 12
Freescale Semiconductor
2-13
2.6.4.4 Hardware Reset Configuration
Hardware reset configuration is enabled if HPE is sampled low at the rising edge of PORESET. The value driven on
RSTCONF
while PORESET changes from assertion to deassertion determines the MSC8103 configuration. If
RSTCONF
is deasserted (driven high) while PORESET changes, the MSC8103 acts as a configuration slave. If
RSTCONF
is asserted (driven low) while PORESET changes, the MSC8103 acts as a configuration master. Section
2.6.4.4, Hardware Reset Configuration, explains the configuration sequence and the terms “configuration master”
and “configuration slave.”
Directly after the deassertion of PORESET and choice of the reset operation mode as configuration master or
configuration slave, the MSC8103 starts the configuration process. The MSC8103 asserts HRESET and SRESET
throughout the power-on reset process, including configuration. Configuration takes 1024 CLOCKIN cycles, after
which MODCK[1–3] are sampled to determine the MSC8103’s working mode.
Next, the MSC8103 halts until the SPLL locks. The SPLL locks according to MODCK[1–3], which are sampled, and
to MODCK_H taken from the Reset Configuration Word. SPLL locking time is 800 reference clocks, which is the
clock at the output of the SPLL Pre-divider. After the SPLL is locked, all the clocks to the MSC8103 are enabled.
If the DLLDIS bit in the reset configuration word is reset, the DLL starts the locking process after the SPLL is
locked. During PLL and DLL locking, HRESET and SRESET are asserted. HRESET remains asserted for another 512
BUS clocks and is then released. The SRESET is released three bus clocks later. If the DLLDIS bit in the reset
configuration word is set, the DLL is bypassed and there is no locking process, thus saving the DLL locking time.
Figure 2-8 shows the power-on reset flow.
Figure 2-8.
Hardware Reset Configuration Timing
PORESET
Internal
HRESET
Input
SRESET
RSTCONF is sampled for
master/slave determination
MODCK[1–3] are sampled.
MODCK_H bits are ready
for PLL.
HRESET/SRESET are
extended for 512/515 bus
clocks, respectively, from PLL
and DLL Lock time.
In reset configuration mode:
reset configuration sequence
occurs in this period.
PLL locks after
800 SPLLMFCLKs. DLL
locks 3073 bus clocks after
PLL is locked.
When DLL is disabled, reset
period is shortened by 3073
bus clocks.
Output (I/O)
1
asserted for
min 16
CLKIN.
2
3
4
PLL locked
DLL locked
5
6
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