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| 型號： | MSC8103VT1200F |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 51/104頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP 16BIT 300MHZ 332-FCPBGA |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | StarCore |
| 類型： | SC140 內(nèi)核 |
| 接口： | 通信處理器模塊（CPM） |
| 時鐘速率： | 300MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 512kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.60V |
| 工作溫度： | -40°C ~ 75°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 332-BFBGA，F(xiàn)CPBGA |
| 供應(yīng)商設(shè)備封裝： | 332-FCBGA（17x17） |
| 包裝： | 托盤 |
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MSC8103 Network Digital Signal Processor, Rev. 12
2-10
Freescale Semiconductor
Physical and Electrical Specifications
2.6.4.1 Reset Operation
The reset control logic determines the cause of a reset, synchronizes it if necessary, and resets the appropriate logic
modules. The memory controller, system protection logic, interrupt controller, and parallel I/O pins are initialized
only on hard reset. Soft reset initializes the internal logic while maintaining the system configuration. The
MSC8103 has three mechanisms for reset configuration: host reset configuration, hardware reset configuration,
and reduced reset configuration.
2.6.4.2 Power-On Reset Flow
Asserting the PORESET external pin initiates the power-on reset flow. PORESET should be asserted externally for at
least 16 input clock cycles after external power to the MSC8103 reaches at least 2/3 VCC. As Table 2-13 shows, the
MSC8103 has five configuration pins, four of which are multiplexed with the SC140 EONCE Event (EE[0–1],
EE[4–5]
) pins and the fifth of which is the RSTCONF pin. These pins are sampled at the rising edge of PORESET. In
addition to these configuration pins, three (MODCK[1–3]) pins are sampled by the MSC8103. The signals on these
pins and the MODCK_H value in the Hard Reset Configuration Word determine the PLL locking mode, by
defining the ratio between the DSP clock, the bus clocks, and the CPM clock frequencies.
Table 2-13.
External Configuration Signals
Pin
Description
Settings
RSTCONF
Reset Configuration
Input line sampled by the MSC8103 at the rising edge of
PORESET.
0
Reset Configuration Master.
1
Reset Configuration Slave.
DBREQ/ EE0
EONCE Event Bit 0
Input line sampled after SC140 core PLL locks. Holding EE0
high when PORESET is deasserted puts the SC140 into
Debug mode.
0
SC140 starts the normal processing
mode after reset.
1
SC140 enters Debug mode immediately
after reset.
HPE/EE1
Host Port Enable
Input line sampled at the rising edge of PORESET. If
asserted, the Host port is enabled, the system data bus is
32-bit wide, and the Host must program the reset
configuration word.
0
Host port disabled (hardware reset
configuration enabled).
1
Host port enabled.
BTM[0–1]/
EE[4–5]
Boot Mode
Input lines sampled at the rising edge of PORESET, which
determine the MSC8103 Boot mode.
00
MSC8103 boots from external memory.
01
MSC8103 boots from HDI16.
10
Reserved.
11
Reserved.
Table 2-14.
Reset Timing
No.
Characteristics
Expression
Min
Max
Unit
1
Required external PORESET duration minimum
CLKIN = 18 MHz
CLKIN = 75 MHz
16
/ CLKIN
888.8
213.3
—
ns
2
Delay from deassertion of external PORESET to deassertion of
internal PORESET
CLKIN = 18 MHz
CLKIN = 75 MHz
1024
/ CLKIN
56.89
13.65
μs
3
Delay from deassertion of internal PORESET to SPLL lock
SPLLMFCLK = 18 MHz
SPLLMFCLK = 25 MHz
800
/ SPLLMFCLK
44.4
32.0
μs
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