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參數(shù)資料
型號： MSC8103VT1200F
廠商： Freescale Semiconductor
文件頁數(shù)： 52/104頁
文件大?。?/td> 0K
描述： IC DSP 16BIT 300MHZ 332-FCPBGA
標準包裝： 90
系列： StarCore
類型： SC140 內核
接口： 通信處理器模塊（CPM）
時鐘速率： 300MHz
非易失內存： 外部
芯片上RAM： 512kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.60V
工作溫度： -40°C ~ 75°C
安裝類型： 表面貼裝
封裝/外殼： 332-BFBGA，F(xiàn)CPBGA
供應商設備封裝： 332-FCBGA（17x17）
包裝： 托盤
AC Timings
MSC8103 Network Digital Signal Processor, Rev. 12
Freescale Semiconductor
2-11
2.6.4.3 Host Reset Configuration
Host reset configuration allows the host to program the reset configuration word via the Host port after PORESET is
deasserted, as described in the MSC8103 Reference Manual. The MSC8103 samples the signals described in Table
2-13 one the rising edge of PORESET when the signal is deasserted.
If HPE is sampled high, the host port is enabled. In this mode the RSTCONF pin must be pulled up. The device
extends the internal PORESET until the host programs the reset configuration word register. The host must write
four 8-bit half-words to the Host Reset Configuration Register address to program the reset configuration word,
which is 32 bits wide. For more information, see the MSC8103 Reference Manual. The reset configuration word is
programmed before the internal PLL and DLL in the MSC8103 are locked. The host must program it after the
rising edge of the PORESET input. In this mode, the host must have its own clock that does not depend on the
MSC8103 clock. After the PLL and DLL are locked, HRESET remains asserted for another 512 bus clocks and is
then released. The SRESET is released three bus clocks later (see Figure 2-7).
4
Delay from SPLL lock to DLL lock
DLL enabled
— BCLK = 18 MHz
— BCLK = 75 MHz
DLL disabled
3073
/ BLCK
—
170.72
40.97
0.0
μs
ns
5
Delay from SPLL lock to HRESET deassertion
DLL enabled
— BCLK = 18 MHz
— BCLK = 75 MHz
DLL disabled
— BCLK = 18 MHz
— BCLK = 75 MHz
3585
/ BLCK
512
/ BLCK
199.17
47.5
28.4
6.83
μs
6
Delay from SPLL lock to SRESET deassertion
DLL enabled
— BCLK = 18 MHz
— BCLK = 75 MHz
DLL disabled
— BCLK = 18 MHz
— BCLK = 75 MHz
3588
/ BLCK
515
/ BLCK
199.33
47.84
28.61
6.87
μs
Note:
Value given for lowest possible CLKIN frequency 18 MHz to ensure proper initialization of reset sequence.
Table 2-14.
Reset Timing (Continued)
No.
Characteristics
Expression
Min
Max
Unit
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