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參數(shù)資料
| 型號： | MSC8103VT1200F |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 21/104頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP 16BIT 300MHZ 332-FCPBGA |
| 標準包裝： | 90 |
| 系列： | StarCore |
| 類型： | SC140 內(nèi)核 |
| 接口： | 通信處理器模塊（CPM） |
| 時鐘速率： | 300MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 512kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.60V |
| 工作溫度： | -40°C ~ 75°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 332-BFBGA，F(xiàn)CPBGA |
| 供應商設備封裝： | 332-FCBGA（17x17） |
| 包裝： | 托盤 |
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CPM Ports
MSC8103 Network Digital Signal Processor, Rev. 12
Freescale Semiconductor
1-19
PA17
FCC1: RXD7
UTOPIA
FCC1: RXD0
MII and HDLC nibble
FCC1: RXD
HDLC serial and transparent
Input
FCC1: UTOPIA Receive Data Bit 7.
The MSC8103 inputs ATM cell octets (UTOPIA interface data) on
RXD[0–7]. RXD7 is the most significant bit. When no ATM data is
available, idle cells are inserted. A cell is 53 bytes. To support Multi-PHY
configurations, RXD[0–7] is tri-stated, enabled only when RXENB is
asserted.
FCC1: MII and HDLC Nibble Receive Data Bit 0
RXD[3–0] is supported by MII and HDLC nibble mode in FCC1. RXD0 is
the least significant bit.
FCC1: HDLC Serial and Transparent Receive Data Bit
This is the single receive data bit supported by HDLC and transparent
modes.
PA16
FCC1: RXD6
UTOPIA
FCC1: RXD1
MII and HDLC nibble
Input
FCC1: UTOPIA Receive Data Bit 6.
The MSC8103 inputs ATM cell octets (UTOPIA interface data) on
RXD[0–7]. This is bit 6 of the receive data. RXD7 is the most significant
bit. When no ATM data is available, idle cells are inserted. A cell is 53
bytes. To support Multi-PHY configurations, RXD[0–7] is tri-stated,
enabled only when RXENB is asserted.
FCC1: MII and HDLC Nibble Receive Data Bit 1
This is bit 1 of the receive nibble data. RXD3 is the most significant bit.
PA15
FCC1: RXD5
UTOPIA
RXD2
MII and HDLC nibble
Input
FCC1: UTOPIA Receive Data Bit 5
The MSC8103 inputs ATM cell octets (UTOPIA interface data) on
RXD[0–7]. This is bit 5 of the receive data. RXD7 is the most significant
bit. When no ATM data is available, idle cells are inserted. A cell is 53
bytes. To support Multi-PHY configurations, RXD[0–7] is tri-stated,
enabled only when RXENB is asserted.
FCC1: MII and HDLC Nibble Receive Data Bit 2
This is bit 2 of the receive nibble data. RXD3 is the most significant bit.
PA14
FCC1: RXD4
UTOPIA
FCC1: RXD3
MII and HDLC nibble
Input
FCC1: UTOPIA Receive Data Bit 4.
The MSC8103 inputs ATM cell octets (UTOPIA interface data) on
RXD[0–7]. RXD7 is the most significant bit. RXD0 is the least significant
bit. When no ATM data is available, idle cells are inserted. A cell is 53
bytes. To support Multi-PHY configurations, RXD[0–7] is tri-stated,
enabled only when RXENB is asserted.
FCC1: MII and HDLC Nibble Receive Data Bit 3
RXD3 is the most significant bit of the receive nibble bit.
PA13
FCC1: RXD3
UTOPIA
SDMA: MSNUM2
Input
Output
FCC1: UTOPIA Receive Data Bit 3
The MSC8103 inputs ATM cell octets (UTOPIA interface data) on
RXD[0–7]. RXD7 is the most significant bit. RXD0 is the least significant
bit. A cell is 53 bytes. To support Multi-PHY configurations, RXD[0–7] is
tri-stated, enabled only when RXENB is asserted.
Module Serial Number Bit 2
The MSNUM has 6 bits that identify devices using the serial DMA
(SDMA) modules. MSNUM[0–4] is the sub-block code of the current
peripheral controller using SDMA. MSNUM5 indicates the section,
transmit (0) or receive (1), that is active during the transfer. The
information is recorded in the SDMA transfer error registers.
Table 1-7.
Port A Signals (Continued)
Name
Dedicated
I/O Data
Direction
Description
General-
Purpose I/O
Peripheral Controller:
Dedicated Signal
Protocol
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