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參數(shù)資料
| 型號(hào)： | MPC970 |
| 廠商： | Motorola, Inc. |
| 英文描述： | LOW VOLTAGE PLL CLOCK DRIVER |
| 中文描述： | 低壓PLL時(shí)鐘驅(qū)動(dòng)器 |
| 文件頁(yè)數(shù)： | 6/16頁(yè) |
| 文件大?。?/td> | 213K |
| 代理商： | MPC970 |
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MPC970
MOTOROLA
TIMING SOLUTIONS
BR1333 — Rev 6
6
AC CHARACTERISTICS
(TA = 0 to 70
°
C)
Symbol
Characteristic
Min
Typ
Max
Unit
Condition
fXtal
Fout
tDC
Crystal Oscillator Frequency
10
25
MHz
Note 3.
Maximum 2x_PCLK Output Frequency
200
MHz
Note 4.
Output Duty Cycle (Notes 4., 5.)
45
35
55
65
%
Fout < 200MHz
Fout
≥
200MHz
VOHAC
AC Output HIGH Voltage
2.4
2.2
V
Fout < 200MHz
Fout
≥
200MHz
VOLAC
AC Output LOW Voltage
0.4
0.6
V
Fout < 200MHz
Fout
≥
200MHz
tpw
tper
fVCO
tjitter
2x_PCLK Pulse Width (Notes 4., 5.)
1.75
2.27
ns
Fout = 200MHz
Fout = 200MHz
Minimum Clock Out Period
4.85
4.91
ns
VCO Lock Range
200
700
MHz
Output Jitter (Notes 4., 5.)
±
50
110
76
±
100
190
210
ps
PLL Jitter
2x_P Period Variation
Period Variation (Other)
tskew
Output–to–Output Skew (Notes 4., 5.)
2x_PCLCK, PCLKEN, BCLKEN, BCLK
2x_PCLK, PCLKEN, BCLK
PCI_CLK
BCLK
All
550
550
450
550
800
ps
MPC601_Clks = ‘0’
MPC601_Clks = ‘1’
tdelay
tr, tf
tlock
tPZL
tPHZ, tPLZ
fMAX
ts
Propagation Delay
2x_PCLK to BCLKEN
100
850
ps
MPC601_Clks = ‘1’
Output Rise/Fall Time (Notes 4., 5.)
0.15
1.5
ns
0.8 to 2.0V
PLL Lock Time
10
ms
Output Enable Time
MR/Tristate to Outputs
8
ns
Output Disable Time
MR/Tristate to Outputs
10
ns
Maximum Frz_Clk Frequency
20
MHz
Setup Time
Frz_Data to Frz_Clk
Com_Frz to Frz_Strobe
8
5
th
Hold Time
Frz_Clk to Frz_Data
Frz_Strobe to Com_Frz
8
5
3. See Applications Info section for more crystal information.
4. Drive 50
transmission lines.
5. Measured at 1.4V.
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