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參數(shù)資料
| 型號： | MPC973 |
| 廠商： | Motorola, Inc. |
| 英文描述： | LOW VOLTAGE PLL CLOCK DRIVER |
| 中文描述： | 低壓PLL時鐘驅(qū)動器 |
| 文件頁數(shù)： | 1/14頁 |
| 文件大小： | 182K |
| 代理商： | MPC973 |
SEMICONDUCTOR TECHNICAL DATA
1
REV 1
Motorola, Inc. 1997
8/97
The MPC972/973 are 3.3V compatible, PLL based clock driver
devices targeted for high performance CISC or RISC processor based
systems. With output frequencies of up to 125MHz and skews of 550ps
the MPC972/973 are ideally suited for most synchronous systems. The
devices offer twelve low skew outputs plus a feedback and sync output for
added flexibility and ease of system implementation.
Fully Integrated PLL
Output Frequency up to 125MHz
Compatible with PowerPC
and Pentium
Microprocessors
TQFP Packaging
3.3V VCC
±
100ps Typical Cycle–to–Cycle Jitter
The MPC972/973 features an extensive level of frequency
programmability between the 12 outputs as well as the input vs output
relationships. Using the select lines output frequency ratios of 1:1, 2:1,
3:1, 3:2, 4:1, 4:3, 5:1, 5:2, 5:3, 6:1 and 6:5 between outputs can be
realized by pulsing low one clock edge prior to the coincident edges of the
Qa and Qc outputs. The Sync output will indicate when the coincident
rising edges of the above relationships will occur. The selectability of the
feedback frequency is independent of the output frequencies, this allows
for very flexible programming of the input reference vs output frequency
relationship. The output frequencies can be either odd or even multiples
of the input reference. In addition the output frequency can be less than
the input frequency for applications where a frequency needs to be
reduced by a non–binary factor. The Power–On Reset ensures proper
programming if the frequency select pins are set at power up. If the
fselFB2 pin is held high, it may be necessary to apply a reset after
power–up to ensure synchronization between the QFB output and the
other outputs. The internal power–on reset is designed to provide this
function, but with power–up conditions being system dependent, it is
difficult to guarantee. All other conditions of the fsel pins will automatically
synchronize during PLL lock acquisition.
The MPC972/973 offers a very flexible output enable/disable scheme. This enable/disable scheme helps facilitate system
debug as well as provide unique opportunities for system power down schemes to meet the requirements of “green” class
machines. The MPC972 allows for the enabling of each output independently via a serial input port. When disabled or “frozen”
the outputs will be locked in the “LOW” state, however the internal state machines will continue to run. Therefore when “unfrozen”
the outputs will activate synchronous and in phase with those outputs which were not frozen. The freezing and unfreezing of
outputs occurs only when they are already in the “LOW” state, thus the possibility of runt pulse generation is eliminated. A
power-on reset will ensure that upon power up all of the outputs will be active. Note that all of the control inputs on the
MPC972/973 have internal pull–up resistors.
The MPC972/973 is fully 3.3V compatible and requires no external loop filter components. All inputs accept LVCMOS/LVTTL
compatible levels while the outputs provide LVCMOS levels with the capability to drive 50
transmission lines. For series
terminated lines each MPC972/973 output can drive two 50
lines in parallel thus effectively doubling the fanout of the device.
The MPC972/973 can consume significant power in some configurations. Users are encouraged to review Application Note
AN1545/D in the Timing Solutions book (BR1333/D) for a discussion on the thermal issues with the MPC family of clock drivers.
PowerPC is a trademark of International Business Machines Corporation. Pentium is a trademark of Intel Corporation.
LOW VOLTAGE
PLL CLOCK DRIVER
FA SUFFIX
52–LEAD TQFP PACKAGE
CASE 848D-03
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PDF描述 |
|---|---|
| MPC974 | 3.3V PLL Clock Driver(3.3V PLL時鐘驅(qū)動器) |
| MPC9774 | 3.3V / 2,5V 1:14 LVCMOS PLL CLOCK GENERATOR |
| MPC980 | Dual 3.3V PLL Clock Generator(雙3.3V PLL時鐘發(fā)生器) |
| MPC9855 | Clock Generator for PowerQUICC and PowerPC Microprocessors |
| MPC992 | Low Voltage PLL Clock Driver(低壓PLL時鐘驅(qū)動器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC974 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
| MPC974A44 F44A WAF | 制造商:Motorola Inc 功能描述: |
| MPC9772 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:3.3V 1:12 LVCMOS PLL Clock Generator |
| MPC9772AE | 功能描述:鎖相環(huán) - PLL 2.5 3.3V 250MHz Clock Generator RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MPC9772AER2 | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 FSL 1-12 LVCMOS PLL Clock Generator, xta RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
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