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參數(shù)資料
| 型號： | MPC970 |
| 廠商： | Motorola, Inc. |
| 英文描述： | LOW VOLTAGE PLL CLOCK DRIVER |
| 中文描述： | 低壓PLL時鐘驅(qū)動器 |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 213K |
| 代理商： | MPC970 |
MPC970
TIMING SOLUTIONS
BR1333 — Rev 6
11
MOTOROLA
Using the On–Board Crystal Oscillator
The MPC970 features an on–board crystal oscillator to
allow for seed clock generaytion as well as final distribution.
The on–board oscillator is completely self contained so that
the only external component required is the crystal. As the
oscillator is somewhat sensitive to loading on its inputs the
user is advised to mount the crystal as close to the MPC970
as possible to avoid any board level parasitics. To facilitate
co–location surface mount crystals are recommended, but
not required. In addition, with crystals with a higher shunt
capacitance, it may be necessary to place a 1k resistor
across the two crystal leads.
The oscillator circuit is a series resonant circuit as
opposed to the more common parallel resonant circuit, this
eliminates the need for large on–board capacitors. Because
the design is a series resonant design for the optimum
frequency accuracy a series resonant crystal should be used
(see specification table below). Unfortunately most off the
shelf crystals are characterized in a parallel resonant mode.
However a parallel resonant crystal is physically no different
than a series resonant crystal, a parallel resonant crystal is
simply a crystal which has been characterized in its parallel
resonant mode. Therefore in the majority of cases a parallel
specified crystal can be used with the MPC970 with just a
minor frequency error due to the actual series resonant
frequency of the parallel resonant specified crystal. Typically
a parallel specified crystal used in a series resonant mode
will exhibit an oscillatory frequency a few hundred ppm lower
than the specified value. For most processor
implementations a few hundred ppm translates into kHz
inaccuracies, a level which does not represent a major issue.
Table 3. Crystal Specifications
Parameter
Value
Crystal Cut
Fundamental at Cut
Resonance
Series Resonance*
Frequency Tolerance
±
75ppm at 25
°
C
Frequency/Temperature Stability
±
150pm 0 to 70
°
C
Operating Range
0 to 70
°
C
Shunt Capacitance
5–7pF
Equivalent Series Resistance (ESR)
50 to 80
Correlation Drive Level
100
μ
W
Aging
5ppm/Yr (First 3 Years)
* See accompanying text for series versus parallel resonant
discussion.
The MPC970 is a clock driver which was designed to
generate outputs with programmable frequency relationships
and not a synthesizer with a fixed input frequency. As a result
the crystal input frequency is a function of the desired output
frequency. For a design which utilizes the external feedback
to the PLL the selection of the crystal frequency is straight
forward; simply chose a crystal which is equal in frequency to
the fed back signal. To determine the crystal required to
produce the desired output frequency for an application
which utilizes internal feedback the block diagram of Figure 8
should be used. The P and the M values for the MPC970 are
also included in Figure 8. The M values can be found in the
configuration tables included in this applications section.
Figure 8. PLL Block Diagram
fref
Phase
Detector
Qn
VCO
LPF
÷
P
÷
N
÷
m
fref
fQn · N · P
m
fref
fVCO
m
,
fVCO
fQn · N · P
m = 32
P = 1 (VCO_Sel=‘1’), 2(VCO_Sel=‘0’)
For the MPC970 clock driver, the following will provide an
example of how to determine the crystal frequency required
for a given design.
Given:
2x_PCLK
= 200MHz
PCLKEN
= 100MHz
BCLK
= 50MHz
PCI_CLK
= 25MHz
VCO_SEL = ‘1’
fref
fQn · N · P
m
From Table 3
PCI_CLK = VCO/16 then N = 16
or
PCLKEN = VCO/4 then N = 4
From Figure 8
m = 32 and P = 1
fref
25 · 16 · 1
32
12.5MHz or100 · 4 · 1
32
12.5MHz
Driving Transmission Lines
The MPC970 clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 10
the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to application note AN1091 in the
Timing Solutions brochure (BR1333/D).
In most high performance clock networks point–to–point
distribution of signals is the method of choice. In a
point–to–point scheme either series terminated or parallel
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