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參數(shù)資料
| 型號： | MPC970 |
| 廠商： | Motorola, Inc. |
| 英文描述： | LOW VOLTAGE PLL CLOCK DRIVER |
| 中文描述： | 低壓PLL時鐘驅動器 |
| 文件頁數(shù)： | 14/16頁 |
| 文件大?。?/td> | 213K |
| 代理商： | MPC970 |
MPC970
MOTOROLA
TIMING SOLUTIONS
BR1333 — Rev 6
14
Driving the PowerPC 603, PowerPC 604 and Pentium
Microprocessors
The PowerPC 603, PowerPC 604 and Pentium
processors differ from the MPC 601 processor in that the
processor input clocks are at the same frequency as the
processor bus. A typical system for these processors will
include 8 – 16 clock loads on the processor bus. When the
MPC970 is taken out of the MPC601_Clk mode there are a
total of 8 “non PCI_CLK” outputs which can be run at the
processor bus speeds for these microprocessors. Since
each output can drive two series terminated transmission
lines the MPC970 can support point to point clock distribution
for up to 16 loads on the processor bus. In addition there will
be 7 PCI_CLK outputs which can drive up to 14 loads on the
PCI bus.
If more clock loads are present on the processor bus the
PCI_CLKs can be configured to drive processor bus clock
loads in addition to the BCLKs or alternatively the clocking
roles of the BCLKs and PCI_CLKs can be reversed. Table 3
illustrates some useful frequency combinations for driving
PowerPC 603, PowerPC 604 or Pentium microprocessor
based systems.
Table Table 5. Common PowerPC 603, PowerPC 604
and Pentium System Frequencies
2x_PCLK
PCLK
BCLK
PCI_CLK
80
75
66
66
66
60
80
75
66
66
66
60
80(1x)
75(1x)
66(1x)
66(1x)
33(1/2x)
60(1x)
26(1/3x)
25(1/3x)
33(1/2x)
66(1x)
66(PCLKEN)
30(1/2x)
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