參數(shù)資料
型號(hào)： MPC8240RZU266X
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 266 MHz, RISC PROCESSOR, PBGA352
封裝： 35 X 35 MM, 1.65 MM HEIGHT, 1.27 MM PITCH, CAVITY DOWN, TBGA-352
文件頁(yè)數(shù)： 6/48頁(yè)
文件大小： 279K
代理商： MPC8240RZU266X
14
MPC8240 Hardware Specifications
MOTOROLA
PRELIMINARY (Rev 0.2) SUBJECT TO CHANGE WITHOUT NOTICE
Notes:
1
These specications are for the default driver strengths indicated in Table 4.
2
Rise and fall times for the PCI_SYNC_IN input are measured from 0.4 to 2.4 V.
3
Specication value at maximum frequency of operation.
4
Relock time is guaranteed by design and characterization. Relock time is not tested.
5
Rise and fall times for the OSC_IN input is guaranteed by design and characterization. OSC_IN input rise
and fall times are not tested.
6
Relock timing is guaranteed by design. PLL-relock time is the maximum amount of time required for PLL
lock after a stable Vdd and PCI_SYNC_IN are reached during the reset sequence. This specication also
applies when the PLL has been disabled and subsequently re-enabled during sleep mode. Also note that
HRST_CPU / HRST_CTRL must be held asserted for a minimum of 255 bus clocks after the PLL-relock
time during the reset sequence.
7
DLL_EXTEND is bit 7 of the PMC2 register <72>. N is a non-zero integer (1, 2, 3, ...). Tclk is the period of
one SDRAM_SYNC_OUT clock cycle in ns. tloop is the propagation delay of the DLL synchronization
feedback loop (PC board runner) from SDRAM_SYNC_OUT to SDRAM_SYNC_IN in ns; 6.25 inches of
loop length (unloaded PC board runner) corresponds to approximately 1 ns of delay. tx0 is a xed delay
inherent in the design when the DLL is at tap point 0 and the DLL is contributing no delay; tx0 equals
approximately 3 ns. See Figure 5 for DLL locking ranges.
2,3
PCI_SYNC_IN Rise and Fall Times
2.0
ns
2
4
PCI_SYNC_IN Duty Cycle Measured at 1.4 V.
40
60
%
5a
PCI_SYNC_IN Pulse Width High Measured at 1.4V
12
18
ns
3
5b
PCI_SYNC_IN Pulse Width Low Measured at 1.4V
12
18
ns
3
7
PCI_SYNC_IN Short Term Jitter (Cycle to Cycle)
<500
ps
8a
PCI_CLK[04] Skew (Pin to Pin)
0
500
ps
8b
SDRAM_CLK[03] Skew (Pin to Pin)
TBD
ps
9
PCI_SYNC_IN Long Term Jitter
<500
ps
10
Internal PLL Relock Time
100
s
3,4,6
DLL Lock Range with DLL_EXTEND = 0 disabled (Default)
0
(NTclk - tloop - tx0) 7ns
7
DLL Lock Range with DLL_EXTEND = 1 enabled
0
(NTclk/2 - tloop - tx0) 7ns
7
Frequency of Operation (OSC_IN)
25
66
MHz
OSC_IN Cycle Time
40
15
ns
OSC_IN Rise and Fall Times
5
ns
5
OSC_IN Duty Cycle Measured at 1.4 V.
40
60
%
OSC_IN Frequency Stability
1000
ppm
OSC_IN Jitter (Cycle to Cycle)
<TBD
ps
OSC_IN VIH (Loaded)
TBD
V
OSC_IN VIL (Loaded)
TBD
V
Table 8. Clock AC Timing Specifications (Continued)
At recommended operating conditions (See Table 2) with GVdd = 3.3 V ± 5% and LVdd = 3.3 V ± 5%
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