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參數(shù)資料
| 型號： | MPC8240RZU266X |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 266 MHz, RISC PROCESSOR, PBGA352 |
| 封裝： | 35 X 35 MM, 1.65 MM HEIGHT, 1.27 MM PITCH, CAVITY DOWN, TBGA-352 |
| 文件頁數(shù)： | 32/48頁 |
| 文件大?。?/td> | 279K |
| 代理商： | MPC8240RZU266X |
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38
MPC8240 Hardware Specifications
MOTOROLA
PRELIMINARY (Rev 0.2) SUBJECT TO CHANGE WITHOUT NOTICE
the maximum potential difference on power-down.
Figure 21. Example Voltage Sequencing Circuits
1.7.3 Decoupling Recommendations
Due to the MPC8240s dynamic power management feature, large address and data buses, and high
operating frequencies, the MPC8240 can generate transient power surges and high frequency noise in its
power supply, especially while driving large capacitive loads. This noise must be prevented from reaching
other components in the MPC8240 system, and the MPC8240 itself requires a clean, tightly regulated
source of power. Therefore, it is recommended that the system designer place at least one decoupling
capacitor at each Vdd, OVdd, GVdd, and LVdd pin of the MPC8240. It is also recommended that these
decoupling capacitors receive their power from separate Vdd, OVdd, GVdd, and GND power planes in the
PCB, utilizing short traces to minimize inductance. These capacitors should have a value of 0.1 F. Only
ceramic SMT (surface mount technology) capacitors should be used to minimize lead inductance,
preferably 0508 or 0603, oriented such that connections are made along the length of the part.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,
feeding the Vdd, OVdd, GVdd, and LVdd planes, to enable quick recharging of the smaller chip capacitors.
These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the quick
response time necessary. They should also be connected to the power and ground planes through two vias
to minimize inductance. Suggested bulk capacitors100330 F (AVX TPS tantalum or Sanyo OSCON).
1.7.4 Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. Unused active low inputs should be tied to OVdd. Unused active high inputs should be connected to
GND. All NC (no-connect) signals must remain unconnected.
Power and ground connections must be made to all external Vdd, OVdd, GVdd, LVdd and GND pins of the
MPC8240.
The PCI_SYNC_OUT signal is intended to be routed halfway out to the PCI devices and then returned to
the PCI_SYNC_IN input of the MPC8240.
The SDRAM_SYNC_OUT signal is intended to be routed halfway out to the SDRAM devices and then
returned to the SDRAM_SYNC_IN input of the MPC8240. The trace length may be used to skew or adjust
the timing window as needed. See Motorola application note AN1794/D for more information on this topic.
1.7.5 Pull-up/Pull-down Resistor Requirements
The data bus input receivers are normally turned off when no read operation is in progress; therefore, they
do not require pull-up resistors on the bus. The data bus signals are: DH[031], DL[031], and PAR[07].
If the 32-bit data bus mode is selected, the input receivers of the unused data and parity bits (DL[031], and
3.3V
MUR420
1N5820
MUR420
1N5820
2.5V
+3.3V
+2.5V
Source
+5V
Source
5V
3.3V
2.5V
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