參數(shù)資料
型號： MPC8240RZU266X
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 266 MHz, RISC PROCESSOR, PBGA352
封裝： 35 X 35 MM, 1.65 MM HEIGHT, 1.27 MM PITCH, CAVITY DOWN, TBGA-352
文件頁數(shù)： 30/48頁
文件大?。?/td> 279K
代理商： MPC8240RZU266X
1D
11101
00110
33
8
66
50
100
125
250
33
8
66
50
100
125
250
33
8
50
125
1.5
(3)
2.5
(5)
1E
11110
TBD
Not
Usab
le
Not
Usab
le
Not
Usab
le
Off
1F
11111
TBD
Not
Usab
le
Not
Usab
le
Not
Usab
le
Off
Notes:
1
Caution:
The
PCI_SYNC_IN
frequency
and
PLL_CFG[04]
settings
m
ust
be
chosen
such
that
the
resulting
per
ipher
al
logic/
memor
y
b
us
frequency
,
CPU
(core)
frequency
,and
PLL
(VCO)
frequencies
do
not
e
xceed
their
respectiv
e
maxim
um
or
minim
um
oper
ating
frequencies
sho
wn
i
n
T
a
b
le
7.
Bold
font
n
umer
ical
pairs
indicate
input
r
ange
limit
and
limiting
par
ameter
.
2
The
processor
HID1
v
alues
only
represent
the
m
ultiplier
of
the
processor
s
PLL
(Memor
y
to
Processor
Multiplier),
thus
m
ultiple
MPC8240
PLL_CFG[0
4]
v
alues
ma
y
ha
v
e
the
same
processor
HID1
v
alue
.This
implies
that
system
softw
are
can
not
read
the
HID1
register
and
associat
e
it
with
a
unique
PLL_CFG[04]
v
alue
.
3
PLL_CFG[04]
settings
not
listed
(01001,
01011,
01101,
01111,
10001,
10011,
10101,
10111,
11001,
and
11011)
are
reser
v
e
d.
4
In
PLL
Bypass
mode
,the
OSC_IN
input
signal
cloc
ks
the
inter
nal
processor
directly
,the
PLL
is
disab
led,
and
the
b
us
mode
is
s
et
f
or
1:1
mode
oper
a-
tion.
This
mode
is
intended
f
or
f
actor
y
use
only
.The
A
C
timing
specications
giv
en
in
this
document
do
not
apply
in
PLL
Bypass
mode
.
5
In
Cloc
k
Off
mode
,no
cloc
king
occurs
inside
the
MPC8240
regardless
of
the
OSC_IN
input.
6
Limited
due
to
maxim
um
memor
y
VCO
=
225
MHz.
7
Limited
due
to
minim
um
CPU
VCO
=
200
MHz.
8
Limited
due
to
minim
um
memor
y
VCO
=
100
MHz.
9
Range
v
alues
are
sho
wn
rounded
do
wn
to
the
nearest
whole
n
umber
(decimal
place
accur
acy
remo
v
ed)
f
or
clar
ity
.
T
a
b
le
17.
MPC8240
Microprocessor
PLL
Configuration
(Continued)
Ref
PLL_
CFG
[04]
1,3
CPU
2
HID1
[04]
266
MHz
P
a
rt
9
250
MHz
P
a
rt
9
200
MHz
P
a
rt
9
Ratios
4,5
PCI
Cloc
k
Input
(PCI_
SYNC_IN)
Rang
e
1
(MHz)
P
eriph
Logic/
Mem
Bus
Cloc
k
Rang
e
(MHz)
CPU
Cloc
k
Rang
e
(MHz)
PCI
Cloc
k
Input
(PCI_
SYNC_IN)
Rang
e
1
(MHz)
P
eriph
Logic/
Mem
Bus
Cloc
k
Rang
e
(MHz)
CPU
Cloc
k
Rang
e
(MHz)
PCI
Cloc
k
Input
(PCI_
SYNC_IN)
Rang
e
1
(MHz)
P
eriph
Logic/
Mem
Bus
Cloc
k
Rang
e
(MHz)
CPU
Cloc
k
Rang
e
(MHz)
PCI
to
Mem
(Mem
VCO)
Multiplier
Mem
to
CPU
(CPU
VCO)
Multiplier
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