參數(shù)資料
型號(hào)： MPC8240RZU266X
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 266 MHz, RISC PROCESSOR, PBGA352
封裝： 35 X 35 MM, 1.65 MM HEIGHT, 1.27 MM PITCH, CAVITY DOWN, TBGA-352
文件頁(yè)數(shù)： 4/48頁(yè)
文件大?。?/td> 279K
代理商： MPC8240RZU266X
12
MPC8240 Hardware Specifications
MOTOROLA
PRELIMINARY (Rev 0.2) SUBJECT TO CHANGE WITHOUT NOTICE
Notes:
1
For DRV_PCI, IOH read from the listing in the pull-up mode, I(Min) column, at the 0.33V label by interpo-
lating between the 0.3 V and 0.4 V table entries current values which corresponds to the PCI VOH = 2.97
= 0.9*LVdd (LVdd = 3.3 V) where Table Entry Voltage = LVdd - PCI VOH.
2
For all others with Ovdd or GVdd = 3.3 V, IOH read from the listing in the pull-up mode, I(Min) column, at
the 0.9 V table entry which corresponds to the VOH = 2.4 V where Table Entry Voltage = O/GVdd - PCI
VOH.
3
For GVdd = 2.5 V, IOH read from the listing in the pull-up mode, I(Min) column, at the TBD V table entry
which corresponds to the VOH = TBD V where Table Entry Voltage = GVdd - VOH.
4
For DRV_PCI, IOL read from the listing in the pull-down mode, I(Max) column, at 0.33 V = PCI VOL =
0.1*LVdd (LVdd = 3.3 V) by interpolating between the 0.3 V and 0.4 V table entries.
5
For all others with OVdd or GVdd = 3.3 V, IOL read from the listing in the pull-down mode, I(Max) column,
at the 0.4 V table entry.
6
For GVdd = 2.5 V, IOL read from the listing in the pull-down mode, I(Max) column, at the TBD V table
entry.
Table 5 provides the power consumption for the MPC8240.
Table 5. Power Consumption
Mode
PCI Bus Clock / Memory Bus Clock
CPU Clock Frequency (MHz)
Units
Notes
33/33
100
33/100
200
33/100
250
33/66
266
66/66
266
66/100
200
66/100
250
Full-On
Typical
TBD
W
1, 5
Maximum
- FP
TBD
W
1, 2
Maximum
- INT
TBD
W
1, 3
Doze
Maximum
TBD
W
1, 4
Nap
Maximum
TBD
mW
1, 4
Sleep
Maximum
TBD
mW
1, 4
Notes:
1
The values do not include I/O Supply Power.
2
Maximum - FP power is measured at Vdd = 2.625V @ 0 C with dynamic power management
enabled while running an entirely cache-resident, contrived sequence of instructions which keep the
execution units maximally busy involving oating point calculations.
3
Maximum - INT power is measured at Vdd = 2.625V @ 0 C with dynamic power management
enabled while running an entirely cache-resident, contrived sequence of instructions which keep the
execution units maximally busy but do not involve oating point calculations.
4
Power saving mode maximums are measured at Vdd = 2.625V @ 0 C while the device is in doze,
nap, or sleep mode.
5
Typical power is an average value measured at Vdd = AVdd = 2.5V, OVdd = 3.3V @ 25 C in a sys-
tem while running a typical application.
6
Note about power supply sizing to be added.
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