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參數(shù)資料
| 型號： | MPC8240RZU266X |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 266 MHz, RISC PROCESSOR, PBGA352 |
| 封裝： | 35 X 35 MM, 1.65 MM HEIGHT, 1.27 MM PITCH, CAVITY DOWN, TBGA-352 |
| 文件頁數(shù)： | 33/48頁 |
| 文件大?。?/td> | 279K |
| 代理商： | MPC8240RZU266X |
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MOTOROLA
MPC8240 Hardware Specifications
39
PRELIMINARY (Rev 0.2) SUBJECT TO CHANGE WITHOUT NOTICE
PAR[47]) will be disabled, and their outputs will drive logic zeros when they would otherwise normally be
driven. For this mode, these pins do not require pull-up resistors, and should be left unconnected by the
system to minimize possible output switching.
The TEST[01] pins require pull-up resistors of 120 Ohms or less connected to OVdd.
It is recommended that the following PCI control signals be pulled up to LVdd with weak pull-up resistors
(2K 10K Ohms): DEVSEL, FRAME, IRDY, LOCK, PERR, SERR, STOP, and TRDY. The resistor values
may need to be adjusted stronger to reduce induced noise on specic board designs.
The following pins have internal pull-up resistors: GNT4/DA5, REQ[03], REQ4/DA4, DL0, FOE, RCS0,
SDRAS, SDCAS, CKE, AS, MCP, MAA[02], PMAA[02], TCK, TDI, TMS, TRST, and TEST2. See
Table 16. MPC8240 Pinout Listing for more information.
The following pins are reset conguration pins: GNT4/DA5, DL0, FOE, RCS0, CKE, AS, MCP, QACK/
DA0, MAA[02], PMAA[02], and PLL_CFG[04]/DA[106]. These pins are sampled during reset to
congure the device.
Any other unused active low input pins should be tied to a logic one level via weak pull-up resistors (2K
10K Ohms) to the appropriate power supply listed in . Unused active high input pins should be tied to GND
via weak pull-down resistors (2K 10K Ohms).
1.7.6 JTAG Conguration Signals
Boundary scan testing is enabled through the JTAG interface signals. (BSDL descriptions of the MPC8240
are available on the internet at www.mot.com/SPS/PowerPC/teksupport/tools/BSDL/) The TRST signal is
optional in the IEEE 1149.1 specication but is provided on all PowerPC implementations. While it is
possible to force the TAP controller to the reset state using only the TCK and TMS signals, more reliable
power-on reset performance will be obtained if the TRST signal is asserted during power-on reset. Since the
JTAG interface is also used for accessing the common on-chip processor (COP) function of PowerPC
processors, simply tying TRST to HRST_CPU/HRST_CTRL is not practical. Note that the two hard reset
signals on the MPC8240 (HRST_CPU and HRST_CTRL) must be asserted and negated together to
guarantee normal operation.
The common on-chip processor (COP) function of PowerPC processors allows a remote computer system
(typically a PC with dedicated hardware and debugging software) to access and control the internal
operations of the processor. The COP interface connects primarily through the JTAG port of the processor,
with some additional status monitoring signals. The COP port requires the ability to independently assert
HRST_CPU/HRST_CTRL or TRST in order to fully control the processor. If the target system has
independent reset sources, such as voltage monitors, watchdog timers, power supply failures, or push-button
switches, then the COP reset signals must be merged into these signals with logic.
The arrangement shown in allows the COP to independently assert HRST_CPU/HRST_CTRL or TRST
while insuring that the target can drive HRST_CPU/HRST_CTRL as well. The COP header shown, adds
many benets including breakpoints, watchpoints, register and memory examination/modication and other
standard debugger features are possible through this interface. Availability of these features can be as
inexpensive as an unpopulated footprint for a header to be added when needed.
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| MPC8241LVR200D | 功能描述:微處理器 - MPU INTEGRATED HOST PROC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
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