參數(shù)資料
型號(hào)： MPC8240RZU266X
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 266 MHz, RISC PROCESSOR, PBGA352
封裝： 35 X 35 MM, 1.65 MM HEIGHT, 1.27 MM PITCH, CAVITY DOWN, TBGA-352
文件頁(yè)數(shù)： 31/48頁(yè)
文件大?。?/td> 279K
代理商： MPC8240RZU266X
MOTOROLA
MPC8240 Hardware Specifications
37
PRELIMINARY (Rev 0.2) SUBJECT TO CHANGE WITHOUT NOTICE
1.7 System Design Information
This section provides electrical and thermal design recommendations for successful application of the
MPC8240.
1.7.1 PLL Power Supply Filtering
The AVdd, AVdd2, and LAVdd power signals are provided on the MPC8240 to provide power to the
peripheral logic/memory bus PLL, the 603e processor PLL, and the SDRAM clock delay-locked loop
(DLL), respectively. To ensure stability of the internal clocks, the power supplied to the AVdd, AVdd2, and
LAVdd input signals should be ltered of any noise in the 500kHz to 10MHz resonant frequency range of
the PLLs. A separate circuit similar to the one shown in Figure 20 using surface mount capacitors with
minimum effective series inductance (ESL) is recommended for each of the AVdd, AVdd2, and LAVdd
power signal pins. Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital
Design: A Handbook of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are
recommended over using multiple values.
The circuits should be placed as close as possible to the respective input signal pins to minimize noise
coupled from nearby circuits. Routing directly as possible from the capacitors to the input signal pins with
minimal inductance of vias is important but proportionately less critical for the LAVdd pin.
Figure 20. PLL Power Supply Filter Circuit
1.7.2 Power Supply Voltage Sequencing
The notes in Table 2 contain cautions illustrated in about the sequencing of the external bus voltages and
internal voltages of the MPC8240. These cautions are necessary for the long term reliability of the part. If
they are violated, the electrostatic discharge (ESD) protection diodes will be forward biased and excessive
current can ow through these diodes. shows a typical ramping voltage sequence where the DC power
sources (voltage regulators and/or power supplies) are connected as shown in Figure 21. The voltage
regulator delay shown in can be zero if the various DC voltage levels are all applied to the target board at
the same time. The ramping voltage sequence shows a scenario in which the Vdd/AVdd/AVdd2/LAVdd
power plane is not loaded as much as the OVdd/GVdd power plane and thus Vdd/AVdd/AVdd2/LAVdd
ramps at a faster rate than OVdd/GVdd.
If the system power supply design does not control the voltage sequencing, the circuit of Figure 21 can be
added to meet these requirements. The MUR420 Schottky diodes of Figure 21 control the maximum
potential difference between the 3.3 bus and internal voltages on power-up and the 1N5820 diodes regulate
Vdd
AVdd, AVdd2, or LAVdd
10
W
2.2 F
GND
Low ESL surface mount capacitors
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