參數(shù)資料
型號: MPC8240RZU266X
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 266 MHz, RISC PROCESSOR, PBGA352
封裝: 35 X 35 MM, 1.65 MM HEIGHT, 1.27 MM PITCH, CAVITY DOWN, TBGA-352
文件頁數(shù): 41/48頁
文件大?。?/td> 279K
代理商: MPC8240RZU266X
46
MPC8240 Hardware Specifications
MOTOROLA
PRELIMINARY (Rev 0.2) SUBJECT TO CHANGE WITHOUT NOTICE
of-merit used for comparing the thermal performance of various microelectronic packaging technologies,
one should exercise caution when only using this metric in determining thermal management because no
single parameter can adequately describe three-dimensional heat ow. The nal die-junction operating
temperature, is not only a function of the component-level thermal resistance, but the system-level design
and its operating conditions. In addition to the component's power consumption, a number of factors affect
the nal operating die-junction temperatureairow, board population (local heat ux of adjacent
components), heat sink efciency, heat sink attach, heat sink placement, next-level interconnect technology,
system air temperature rise, altitude, etc.
Due to the complexity and the many variations of system-level boundary conditions for today's
microelectronic equipment, the combined effects of the heat transfer mechanisms (radiation, convection and
conduction) may vary widely. For these reasons, we recommend using conjugate heat transfer models for
the board, as well as, system-level designs. To expedite system-level thermal analysis, several compact
thermal-package models are available within FLOTHERM¨. These are available upon request.
1.8 Document Revision History
Table 18 provides a revision history for this hardware specication.
1.9 Ordering Information
This section provides the part numbering nomenclature for the MPC8240. Note that the individual part
numbers correspond to a maximum processor core frequency. For available frequencies, contact your local
Motorola sales ofce.
Table 18. Document Revision History
Document Revision
Substantive Change(s)
0
Preliminary release with some TBDs in the spec tables.
0.1
Updated notes for Table 2.
Replaced TBDs in Table 3 with values for Output High and Low Voltages.
Deleted 25/25/75 column from Table 5; inconsistent with PLL encoding 01000.
Updated minimum processor frequencies in Table 7 from 80 MHz to 100 MHz.
Updated values in Table 9. Input AC Timing Specications. Spec 10b split for Flow
Through and Registered modes.
Updated values in Table 10. Output AC Timing Specications.
Updated PCI_HOLD_DEL value guidelines in Table 11 and Figure 10.
Relabeled DA[015] pins in opposite order and added Note 11 for TEST2 in Table 16.
Changed PLL congurations 01001 and 10001 in Table 17 to reserved congurations.
Updated PLL conguration 00010s operation ranges in Table 17.
Revised TRST connection recommendations in Figure 20 for COP interface.
0.2
Added Note 4 to Table 2, updated Note and Caution numbers in Table 2 and Figure 2.
Modied Table 7:
- Added 250 MHz column.
- Changed maximum PCI Input Frequency for 200 MHz part from 33 MHz to 66 MHz.
- Made one column common entries for Memory Bus and PCI Input Frequencies.
Revised Note 7 of Table 8 to indicate a feedback loop length of 6.25 inches (formerly
11.8 inches) corresponds to approximately 1 ns of delay.
Added 250 MHz column to Table 17.
Corrected Document Revision number for previous version of this document in
Table 18. Document Revision was indicated as 1, should have been 0.1.
Removed P = Reduced Spec information from Figure 27; does not apply to MPC8240.
Added R = Modied Voltage Spec information to Figure 27.
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