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| 型號： | MPC7410VS500LE |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 5/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU PPC 500MHZ 360-FCCLGA |
| 標(biāo)準(zhǔn)包裝： | 44 |
| 系列： | MPC74xx |
| 處理器類型： | 32-位 MPC74xx PowerPC |
| 速度： | 500MHz |
| 電壓： | 1.8V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 360-CLGA，F(xiàn)CCLGA |
| 供應(yīng)商設(shè)備封裝： | 360-FCCLGA（25x25） |
| 包裝： | 托盤 |
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MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
Freescale Semiconductor
13
Electrical and Thermal Characteristics
Table 6 provides the power consumption for the MPC7410.
4.2
AC Electrical Characteristics
This section provides the AC electrical characteristics for the MPC7410. After fabrication, functional parts are
sorted by maximum processor core frequency, see Section 4.2.1, “Clock AC Specifications,” and tested for
conformance to the AC specifications for that frequency. The processor core frequency is determined by the bus
(SYSCLK) frequency and the settings of the PLL_CFG[0:3] signals. Parts are sold by maximum processor core
frequency; see Section 10, “Ordering Information.”
Table 6. Power Consumption for MPC7410
Processor (CPU) Frequency
Unit
Notes
400 MHz
450 MHz
500 MHz
Full-On Mode
Typical
4.2
4.7
5.3
W
1, 3
Maximum
9.5
10.7
11.9
W
1, 2
Doze Mode
Maximum
4.3
4.8
5.3
W
1
Nap Mode
Maximum
1.35
1.5
1.65
W
1
Sleep Mode
Maximum
1.3
1.45
1.6
W
1
Sleep Mode—PLL and DLL Disabled
Typical
600
mW
1
Maximum
1.1
W
1
Notes:
1. These values apply for all valid processor bus and L2 bus ratios. The values do not include I/O supply power (OVDD
and L2OVDD) or PLL/DLL supply power (AVDD and L2AVDD). OVDD and L2OVDD power is system dependent, but
is typically <5% of VDD power. Worst case power consumption for AVDD = 15 mW and L2AVDD =15 mW.
2. Maximum power is measured at 105°C and VDD = 1.8 V while running an entirely cache-resident, contrived
sequence of instructions which keep the execution units, including AltiVec, maximally busy.
3. Typical power is an average value measured at 65°C and VDD = 1.8 V in a system while running typical benchmarks.
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