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| 型號： | MPC7410VS500LE |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 31/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU PPC 500MHZ 360-FCCLGA |
| 標(biāo)準(zhǔn)包裝： | 44 |
| 系列： | MPC74xx |
| 處理器類型： | 32-位 MPC74xx PowerPC |
| 速度： | 500MHz |
| 電壓： | 1.8V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 360-CLGA，F(xiàn)CCLGA |
| 供應(yīng)商設(shè)備封裝： | 360-FCCLGA（25x25） |
| 包裝： | 托盤 |
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MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
Freescale Semiconductor
37
System Design Information
existing designs should qualify both AVDD filter solutions, and the filter providing the most robust margin should
be implemented.
Figure 21. PLL Power Supply Filter Circuit No.1
Figure 22. PLL Power Supply Filter Circuit No. 2
The filter circuit should be placed as close as possible to the AVDD pin to minimize noise coupled from nearby
circuits. A separate circuit should be placed as close as possible to the L2AVDD pin. It is often possible to route
directly from the capacitors to the AVDD pin, which is on the periphery of the 360 BGA footprint, without the
inductance of vias. The L2AVDD pin may be more difficult to route, but is proportionately less critical.
It is the recommendation of Freescale, that systems that implement the AVDD filter shown in Figure 22 design in the
pads for the removed capacitors (shown in Figure 21), to provide for the possible reintroduction of the filter in
Figure 21. This would be necessary in case there is a planned transition from the CBGA package to the HCTE
package of the MPC7410.
8.3 Decoupling Recommendations
Due to the MPC7410 dynamic power management feature, large address and data buses, and high operating
frequencies, the MPC7410 can generate transient power surges and high frequency noise in its power supply,
especially while driving large capacitive loads. This noise must be prevented from reaching other components in the
MPC7410 system, and the MPC7410 itself requires a clean, tightly regulated source of power. Therefore, it is
recommended that the system designer place at least one decoupling capacitor at each VDD, OVDD, and L2OVDD
pin of the MPC7410. It is also recommended that these decoupling capacitors receive their power from separate
VDD, (L2)OVDD, and GND power planes in the PCB, utilizing short traces to minimize inductance.
These capacitors should have a value of 0.01 or 0.1 F. Only ceramic SMT (surface mount technology) capacitors
should be used to minimize lead inductance, preferably 0508 or 0603 orientations, where connections are made
along the length of the part.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the
VDD, L2OVDD, and OVDD planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors
should have a low ESR (equivalent series resistance) rating to ensure the quick response time necessary. They should
also be connected to the power and ground planes through two vias to minimize inductance. Suggested bulk
capacitors—100–330 F (AVX TPS tantalum or Sanyo OSCON).
VDD
AVDD (or L2AVDD)
10
Ω
2.2 F
GND
Low ESL Surface Mount Capacitors
VDD
AVDD
51
Ω
GND
Capacitor
Pad Sites
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