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| 型號： | MPC7410VS500LE |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 45/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU PPC 500MHZ 360-FCCLGA |
| 標(biāo)準(zhǔn)包裝： | 44 |
| 系列： | MPC74xx |
| 處理器類型： | 32-位 MPC74xx PowerPC |
| 速度： | 500MHz |
| 電壓： | 1.8V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 360-CLGA，F(xiàn)CCLGA |
| 供應(yīng)商設(shè)備封裝： | 360-FCCLGA（25x25） |
| 包裝： | 托盤 |
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MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
Freescale Semiconductor
5
Features
— Store gathering
— Executes the cache and TLB instructions
— Big- and little-endian byte addressing supported
— Misaligned little-endian supported
— Supports FXU, FPU, and AltiVec load/store traffic
— Complete support for all four architecture AltiVec DST streams
Level 1 (L1) cache structure
— 32 Kbyte, 32-byte line, eight-way set-associative instruction cache (iL1)
— 32 Kbyte, 32-byte line, eight-way set-associative data cache (dL1)
— Single-cycle cache access
— Pseudo least-recently-used (LRU) replacement
— Data cache supports AltiVec LRU and transient instructions algorithm
— Copy-back or write-through data cache (on a page-per-page basis)
— Supports all PowerPC memory coherency modes
— Nonblocking instruction and data cache
— Separate copy of data cache tags for efficient snooping
— No snooping of instruction cache except for ICBI instruction
Level 2 (L2) cache interface
— Internal L2 cache controller and tags; external data SRAMs
— 512-Kbyte, 1-Mbyte, and 2-Mbyte two-way set-associative L2 cache support
— Copy-back or write-through data cache (on a page basis, or for all L2)
— 32-byte (512-Kbyte), 64-byte (1-Mbyte), or 128-byte (2-Mbyte) sectored line size
— Supports pipelined (register-register) synchronous BurstRAMs and pipelined (register-register) late
write synchronous BurstRAMs
— Supports direct-mapped mode for 256 Kbytes, 512 Kbytes, 1 Mbyte, or 2 Mbytes of SRAM (either all,
half, or none of L2 SRAM must be configured as direct-mapped)
— Core-to-L2 frequency divisors of ÷1, ÷1.5, ÷2, ÷2.5, ÷3, ÷3.5, and ÷4 supported
— 64-bit data bus which also supports 32-bit bus mode
— Selectable interface voltages of 1.8 and 2.5 V
Memory management unit
— 128-entry, two-way set-associative instruction TLB
— 128-entry, two-way set-associative data TLB
— Hardware reload for TLBs
— Four instruction BATs and four data BATs
— Virtual memory support for up to 4 hexabytes (2
52) of virtual memory
— Real memory support for up to 4 gigabytes (232) of physical memory
— Snooped and invalidated for TLBI instructions
Efficient data flow
— All data buses between VRF, load/store unit, dL1, iL1, L2, and the bus are 128 bits wide
— dL1 is fully pipelined to provide 128 bits/cycle to/from the VRF
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