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| 型號： | MPC7410VS500LE |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 29/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU PPC 500MHZ 360-FCCLGA |
| 標準包裝： | 44 |
| 系列： | MPC74xx |
| 處理器類型： | 32-位 MPC74xx PowerPC |
| 速度： | 500MHz |
| 電壓： | 1.8V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 360-CLGA，F(xiàn)CCLGA |
| 供應(yīng)商設(shè)備封裝： | 360-FCCLGA（25x25） |
| 包裝： | 托盤 |
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MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
Freescale Semiconductor
35
System Design Information
The MPC7410 generates the clock for the external L2 synchronous data SRAMs by dividing the core clock
frequency of the MPC7410. The divided-down clock is then phase-adjusted by an on-chip delay-lock-loop (DLL)
circuit and should be routed from the MPC7410 to the external RAMs. A separate clock output, L2SYNC_OUT is
sent out half the distance to the SRAMs and then returned as an input to the DLL on pin L2SYNC_IN so that the
rising-edge of the clock as seen at the external RAMs can be aligned to the clocking of the internal latches in the L2
bus interface.
The core-to-L2 frequency divisor for the L2 PLL is selected through the L2CLK bits of the L2CR register. Generally,
the divisor must be chosen according to the frequency supported by the external RAMs, the frequency of the
0111
4.5x
2x
—
375
(750)
450
(900)
—
1011
5x
2x
—
—375
(750)
416
(833)
500
(1000)
—
1001
5.5x
2x
—
366
(733)
412
(825)
458
(916)
—
1101
6x
2x
—
400
(800)
450
(900)
500
(1000)
—
0101
6.5x
2x
—
433
(866)
488
(967)
—
0010
7x
2x
—
350
(700)
466
(933)
—
0001
7.5x
2x
—
375
(750)
500
(1000)
—
1100
8x
2x
—
400
(800)
—
0000
9x
2x
—
450
(900)
—
0011
PLL off/bypass
PLL off, SYSCLK clocks core circuitry directly, 1x bus-to-core implied
1111
PLL off
PLL off, no core clocking occurs
Notes:
1. PLL_CFG[0:3] settings not listed are reserved.
2. The sample bus-to-core frequencies shown are for reference only. Some PLL configurations may select bus, core,
or VCO frequencies which are not useful, not supported, or not tested for by the MPC7410; see Section 4.2.1,
“Clock AC Specifications,” for valid SYSCLK, core, and VCO frequencies.
3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the
bus mode is set for 1:1 mode operation. This mode is intended for factory use and third-party emulator tool
development only.
Note: The AC timing specifications given in this document do not apply in PLL-bypass mode.
4. In PLL-off mode, no clocking occurs inside the MPC7410 regardless of the SYSCLK input.
5. PLL-off mode should not be used during chip power-up sequencing.
Table 13. MPC7410 Microprocessor PLL Configuration (continued)
PLL_CFG
[0:3]
Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)
Bus-to-
Core
Multiplier
Core-to
VCO
Multiplier
Bus
33.3 MHz
Bus
50 MHz
Bus
66.6 MHz
Bus
75 MHz
Bus
83.3 MHz
Bus
100 MHz
Bus
133 MHz
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