參數(shù)資料
型號: MPC7410VS500LE
廠商: Freescale Semiconductor
文件頁數(shù): 36/56頁
文件大小: 0K
描述: IC MPU PPC 500MHZ 360-FCCLGA
標(biāo)準(zhǔn)包裝: 44
系列: MPC74xx
處理器類型: 32-位 MPC74xx PowerPC
速度: 500MHz
電壓: 1.8V
安裝類型: 表面貼裝
封裝/外殼: 360-CLGA,F(xiàn)CCLGA
供應(yīng)商設(shè)備封裝: 360-FCCLGA(25x25)
包裝: 托盤
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
Freescale Semiconductor
41
System Design Information
Figure 25. COP Connector Diagram
HRESET
HRESET 6
From Target
Board Sources
HRESET
13
SRESET
NC
11
VDD_SENSE
6
5 1
15
2 k
Ω
10 k
Ω
10 k
Ω
10 k
Ω
OVDD
CHKSTP_IN
8
TMS
TDO
TDI
TCK
TMS
TDO
TDI
TCK
9
1
3
4
TRST
7
16
2
10
12
(if any)
COP
He
ader
14 2
Key
QACK
OVDD
10 k
Ω
OVDD
10 k
Ω
OVDD
10 k
Ω
10 k
Ω
QACK
CHKSTP_OUT
3
13
9
5
1
6
10
2
15
11
7
16
12
8
4
KEY
No Pin
COP Connector
Physical Pin Out
10 k
Ω 4
OVDD
1
2 k
Ω 3
0
Ω 5
Notes:
1. RUN/STOP, normally found on pin 5 of the COP header, is not implemented on the MPC7410. Connect
pin 5 of the COP header to OVDD with a 10-kΩ pull-up resistor.
2. Key location; pin 14 is not physically present on the COP header.
3. Component not populated. Populate only if debug tool does not drive QACK.
4. Populate only if debug tool uses an open-drain type output and does not actively negate QACK.
5. If the JTAG interface is implemented, connect HRESET from the target source to TRST from the COP
header though an AND gate to TRST of the part. If the JTAG interface is not implemented, connect
HRESET from the target source to TRST of the part through a 0-
Ω isolation resistor.
6. The COP port and target board should be able to independently assert HRESET and TRST to the pro-
cessor in order to fully control the processor as shown above.
TRST 6
10 k
Ω
OVDD
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