Section 1.3 " />
參數(shù)資料
型號: MPC7410VS500LE
廠商: Freescale Semiconductor
文件頁數(shù): 47/56頁
文件大?。?/td> 0K
描述: IC MPU PPC 500MHZ 360-FCCLGA
標(biāo)準(zhǔn)包裝: 44
系列: MPC74xx
處理器類型: 32-位 MPC74xx PowerPC
速度: 500MHz
電壓: 1.8V
安裝類型: 表面貼裝
封裝/外殼: 360-CLGA,F(xiàn)CCLGA
供應(yīng)商設(shè)備封裝: 360-FCCLGA(25x25)
包裝: 托盤
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
Freescale Semiconductor
51
Document Revision History
1.0
Section 1.3 and Table 3—revised OVDD from 3.3 V ± 100 mV to 3.3 V ± 165 mV.
Table 13—removed unsupported PLL configurations.
Table 12—added note 15 for minimum MCP pulse width, correct note 3 for 3.3-V processor bus
support.
Table 13—revised note 3 to include emulator tool development.
Table 14—removed unsupported Core-to-L2 example frequencies.
Section 1.8.8—updated heat sink vendors list.
Section 1.8.8.2—updated interface vendors list.
Table 1—updated voltage sequencing requirements notes 3 and 4.
Table 4—Updated/added thermal characteristics.
Table 5—removed table and TAU related information, TAU is no longer supported.
Table 6—updated Iin and ITSI leakage current specs.
Section 1.8.3—removed section.
Section 1.10—reformatted section.
Section 1.8.6—changed recommended pull-up resistor value to 1 kW–5 kW. Added AACK, TEA, and
TS to control signals needing pull-ups. Added pull-up resistor value recommendation for
L1_TSTCLK, L2_TSTCLK, and LSSD_MODE factory test signals.
Section 1.8.7—revised text regarding connection of TRST. Combined Figure 22, Figure 23, and Table
17, into Figure 21.
Table 7—corrected min VCO frequencies from 450 to 700 MHz to match min processor frequency of
350 MHz.
Table 2—added note 3 to clarify BVSEL for revisions prior to Rev. E which do not support 3.3 V OVDD.
Table 3—added notes 5 and 6 to clarify BVSEL for revisions prior to Rev. E which do not support 3.3 V
OVDD.
Table 5—added note 8 regarding DC voltage limits for JTAG signals.
Table 16. Document Revision History (continued)
Revision
Date
Substantive Change(s)
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