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| 型號： | MCTSD01-V100 |
| 廠商： | Lineage Power |
| 英文描述： | SDRAM Controller(同步動態(tài)RAM控制器) |
| 中文描述： | SDRAM控制器（同步動態(tài)內(nèi)存控制器） |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 417K |
| 代理商： | MCTSD01-V100 |
January 99
SDRAM Controller
MACRO
MCTSD01-V100
Data Sheet
Logic Design Solution
9/12
1.5.4
State Machine
The simplified diagram of the State Machine is as follows :
1.6 Read and Write cycle
As shown above, the SDRAM Controller is not available in three cases :
-
during the initialization phase after power-up,
-
in Self-Refresh mode,
-
every 15.6μs during the Auto-Refresh cycle for TRC time.
The SDRAM Controller is stated to be not available also in read or write cycle because the SDRAM is used. This feature
could be useful in case of sharing the SDRAM Controller.
If the microprocessor tries to access the SDRAM when the SDRAM controller is not available, it will not get access until
the end of the concerned phase. It means the microprocessor should wait or delay its cycle until the end of the phase.
In order for the microprocessor to manage thess three phases, the SDRAM Controller provides two signals :
SDRAM_AVB and ACCESS_ACK.
SDRAM_AVB signal indicates the availability of the SDRAM Controller at any time. This signal is mainly useful for
identifying the end of the initialization phase.
ACCESS_ACK signal indicates the microprocessor access request is being executed. This signal is useful to generate the
microprocessor wait state signal.
The time between the ACCESS_ACK signal and the generated data is fixed.
Read cycle : 7 periods between the ACCESS_ACK signal and the first data read from the SDRAM.
Write cycle : 4 periods between the ACCESS_ACK signal and the first data written to the SDRAM.
These delays could be verified with the VHDL test bench provided.
SDRAM
INIT
WAIT
REQ
SELF
REF
READ
WRITE
AUTO
REF
SDRAM Not
Available
SDRAM Not
Available
SDRAM Not
Available
Reset
SDRAM Not
Available
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