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參數(shù)資料
| 型號： | MCTSD01-V100 |
| 廠商： | Lineage Power |
| 英文描述： | SDRAM Controller(同步動態(tài)RAM控制器) |
| 中文描述： | SDRAM控制器（同步動態(tài)內(nèi)存控制器） |
| 文件頁數(shù)： | 8/12頁 |
| 文件大小： | 417K |
| 代理商： | MCTSD01-V100 |
January 99
SDRAM Controller
MACRO
MCTSD01-V100
Data Sheet
Logic Design Solution
8/12
The table below shows how addressing differs between 16- and 64-Mbit devices :
Architecture (Mbits)
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
64, four-bank RA
16, two-bank RA
B
X
B
X
Add
B
Add
Add
Add
Add
Add
Add
Add
Add
Add
Add
Add
Add
Add
Add
Add
Add
Add
Add
Add
Add
Add
Add
64, 16-bit CA
64, 8-bit CA
64, 4-bit CA
B
B
B
B
B
B
X
X
X
C
C
C
X
X
X
Add
Add
Add
Add
Add
Add
Add
Add
Add
Add
Add
Add
Add
Add
Add
Add
Add
Add
Add
Add
Add
Add
Add
Add
Add
Add
Add
16, 16-bit CA
16, 8-bit CA
16, 4-bit CA
X
X
X
X
X
X
B
B
B
C
C
C
X
X
X
Add
Add
Add
Add
Add
Add
Add
Add
Add
Add
Add
Add
Add
Add
Add
Add
Add
Add
Add
Add
Add
Add
Add
Add
Add
Add
Add
Notes :
RA
=row address.
B
=bank-select bit.
CA
=column address.
C
=command-control bit used during column-address time.
Add
=valid-address bit.
X
=unused bit.
1.5.3
Timing to respect
For it work properly, the SDRAM Controller requires SDRAMs that meet the specification in the following table :
TIMING
T_RP
DESIGNATION
Read/Write To Precharge
Precharge to Activ
Activ to Precharge
Activ to Activ
Ref to Ref
Ref to Activ
Self_Ref to Ref
Self_Ref to Activ
Writa to Activ
Reada to Activ
Activ to Reada or Writa
Mrs to Activ
DQM to Data out
100 MHz *
3
T_RAS
T_RC
6
9
T_XSR
T_IAPW
T_IAPR
T_RCD
T_MRS
T_DOD
2
5
1
3
1
2
* Unit in clock cycle period = 10 ns.
The State Machine manages all these delays.
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