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參數(shù)資料
| 型號(hào)： | MCTSD01-V100 |
| 廠商： | Lineage Power |
| 英文描述： | SDRAM Controller(同步動(dòng)態(tài)RAM控制器) |
| 中文描述： | SDRAM控制器（同步動(dòng)態(tài)內(nèi)存控制器） |
| 文件頁(yè)數(shù)： | 4/12頁(yè) |
| 文件大?。?/td> | 417K |
| 代理商： | MCTSD01-V100 |
January 99
SDRAM Controller
MACRO
MCTSD01-V100
Data Sheet
Logic Design Solution
4/12
1.3 Pin Description
Signal
CLOCK
Direction
Input
Input
Input
Description
System clock. Rising edge triggered.
Active low. System asynchronous reset of the FPGA.
The CPU asks the SDRAM to enter in Self_Refresh state.
1 = enter in mode. 0 = output of the mode.
Active high. The CPU begin an SDRAM cycle. This cycle is effective when the
positive pulse ACCES_ACK is generated. The ACCES_REQ signal should be
present until the ACCES_ACK signal becomes high.
1 = Read. 0 = Write. Must be present until the end of SDRAM data phase.
Active high. Define a burst cycle. Must be present until the end of SDRAM data
phase.
Active high. Defines which byte in the SDRAM data bus should be validated
especially in write cycle. Must be present until the end of SDRAM data phase.
Active high. Define System address lines.
ASYNC_RESET
SELF_REFRESH
ACCESS_REQ
Input
R_W_SDRAM
BURST
Input
Input
BYTE_ENABLE
Input
MICRO_ADDRESS
Input
SDRAM_AVB
Output
Active high. Indicates that the SDRAM is available. The SDRAM is available when
the SDRAM Controller is in IDLE state.
Active high. Positive pulse which indicates that the SDRAM controller is going to
execute a cycle.
ACCESS_ACK
Output
ADR
RAS
CAS
WE
CKE
DQML /U
Output
Output
Output
Output
Output
Output
Active high. Multiplexed row and column address of the SDRAM.
Active low. RAS signal of the SDRAM.
Active low. CAS signal of the SDRAM.
Active low. WE signal of the SDRAM.
Active low. CKE signal of the SDRAM.
Active low. DQML /U signal of the SDRAM.
The CS pin of the SDRAM device has to be pulled down by the user.
1.4 Functional Description
SDRAM
Address
Multiplexer
SDRAM
Control
Signal
State
Machine
Micro Address
Self_Refresh
Access_Req
R_W_SDRAM
Burst
Byte_Enable
SDRAM_Avb
Access_Ack
Clock
Async_Reset
AD_SDRAM
RAS
CAS
WE
CKE
DQML/U
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