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參數(shù)資料
| 型號： | MCTSD01-V100 |
| 廠商： | Lineage Power |
| 英文描述： | SDRAM Controller(同步動態(tài)RAM控制器) |
| 中文描述： | SDRAM控制器（同步動態(tài)內(nèi)存控制器） |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 417K |
| 代理商： | MCTSD01-V100 |
January 99
SDRAM Controller
MACRO
MCTSD01-V100
Data Sheet
Logic Design Solution
7/12
1.5.2
SDRAM address Multiplexer
The multiplexer mode is for 16-Mbit SDRAM devices. In order to access 64-Mbit SDRAM devices, two address bits (A13,
A12) and hence, two FPGA output pins have to be added. The Design Document gives details about the modification
needed.
The full SDRAM address is composed of two 12-bit addresses. One 12-bit row address and one 12-bit column address.
The 12-bit row address are composed of eleven general address bits : A0 to A10, and one internal bank select bit : A11.
The 12-bit column address is composed of ten general address bits : A0 to A9, one command bit : A10, and one internal
bank select bit : A11. This one is the same as in the row address.
As mentioned above, the SDRAM multiplexer is used also to generate the data of the MRS command.
The default micro address affectation is as follows :
MICRO ADDRESS
A0 =>
A1 =>
A2 =>
A3 =>
A4 =>
A5 =>
A6 =>
A7 =>
A8 =>
A9 =>
A10 =>
A11 =>
A12 =>
A13 =>
A14 =>
A15 =>
A16 =>
A17 =>
A18 =>
A19 - B.S. =>
COLUMN
A0
A1
A2
A3
A4
A5
A6
A7
0
0
Cd. bit
B.S.
ROW
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
B.S.
B.S.
: A19 micro address bit, defines the internal Bank Selection.
Cd.
: Command bit generated by the state machine.
It should be noted that the user has to connect the right address portion to the micro address bus according to the data
size.
For example, in 64-bit data size, the bit A3 of the user microprocessor should be connected to A0 of the micro address
bus, and so on. Microprocessor bits A0 to A2, should be used to generate the Byte Enable signals.
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