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參數(shù)資料
| 型號(hào)： | MCTSD01-V100 |
| 廠商： | Lineage Power |
| 英文描述： | SDRAM Controller(同步動(dòng)態(tài)RAM控制器) |
| 中文描述： | SDRAM控制器（同步動(dòng)態(tài)內(nèi)存控制器） |
| 文件頁(yè)數(shù)： | 10/12頁(yè) |
| 文件大?。?/td> | 417K |
| 代理商： | MCTSD01-V100 |
January 99
SDRAM Controller
MACRO
MCTSD01-V100
Data Sheet
Logic Design Solution
10/12
1.7 I/O Timing Requirement
1.7.1
SDRAM Timing
The main four I/O timing features of four 16-Mbit SDRAM manufacturers are detailed here.
The timings are given for a 10ns clock period (100Mhz) and CAS Latency = 3.
Hitachi Source :
SETUP
-10
2ns min
-8
HOLD IN
1ns min
-
CK TO OUT
8ns max
-
HOLD OUT
3ns min
-
-
Micron Source :
SETUP
-10
3ns min
-8A
2ns min
HOLD IN
1ns min
1ns min
CK TO OUT
7.5ns max
6ns max
HOLD OUT
3ns min
3ns min
NEC Source :
SETUP
2.5ns min
-
HOLD IN
1ns min
-
CK TO OUT
8ns max
-
HOLD OUT
4ns min
-
-10
-8
Siemens Source :
SETUP
-10
3ns min
-8
2ns min
HOLD IN
1ns min
1ns min
CK TO OUT
7ns max
6ns max
HOLD OUT
3ns min
3ns min
Please refer to each Manufacturer’s Data Sheet for details.
1.7.2
FPGA to SDRAM Timing requirement
The FPGA_Clock_to_Out timing parameter must respect the following equations :
FPGA_Ck_to_Out = ( Clock_period ) – ( SDRAM_Setup)
FPGA_Ck_to_Out = 10 ns – (3ns or 2ns)
FPGA_Ck_to_Out = 7 ns or 8 ns
The Lucent Orca Data Sheet (sept 98) provides the following timings :
FPGA CLOCK TO OUT TIMING
ORCA 2T06A-7
ORCA 2T10A-7
ORCA 2T15A-7
ORCA 2T26A-7
ORCA 2T40A-7
REQUISITE SDRAM SETUP TIME
From 3.3 ns to 3.6 ns
From 2.7 ns to 3.2 ns
From 2.2 ns to 2.9 ns
From 1.7 ns to 2.7 ns
From 0.4 ns to 2 ns
6.4 to 6.7 ns
6.8 to 7.3 ns
7.1 to 7.8 ns
7.3 to 8.3 ns
8 to 9.6 ns
ORCA 3T20A-6
ORCA 3T30A-6
ORCA 3T55A-6
ORCA 3T80A-6
ORCA 3T125A-6
ORCA 3T160A-6
----------- *
----------- *
6.16 to 6.91 ns *
6.40 to 7.3 ns *
----------- *
----------- *
From 3.09 ns to 3.84 ns
From 2.7 ns to 3.6 ns
* Express Clock used.
Please refer to the Manufacturer’s Data Sheet for details.
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