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參數(shù)資料
| 型號(hào)： | MCTSD01-V100 |
| 廠商： | Lineage Power |
| 英文描述： | SDRAM Controller(同步動(dòng)態(tài)RAM控制器) |
| 中文描述： | SDRAM控制器（同步動(dòng)態(tài)內(nèi)存控制器） |
| 文件頁(yè)數(shù)： | 5/12頁(yè) |
| 文件大?。?/td> | 417K |
| 代理商： | MCTSD01-V100 |
January 99
SDRAM Controller
MACRO
MCTSD01-V100
Data Sheet
Logic Design Solution
5/12
The SDRAM Controller is composed of three main functions.
The State Machine is the heart of the Controller, and is in charge of generating the right sequence of SDRAM control
signals.
The SDRAM address multiplexer is in charge of generating the Row and Column address, and also the data of the SDRAM
MRS command.
The SDRAM Control signals is in charge of generating the Control signals.
1.5 SDRAM Controller philosophy
The SDRAM Controller is capable of managing 4 SDRAM memory devices.
To reduce the complexity of the Controller, this one uses Read and Write with Auto-precharge Command.
The default configuration of the Controller is as follows :
-
-
-
-
-
Read and Write with Burst enabled.
CAS Latency : 3.
Burst type : Sequential.
Burst Length : 4 data.
10ns or 8 ns SDRAM devices required.
Logic Design Solutions as the user can modify the Burst length to 2, 4 or 8, as SDRAM device enables it. The full page
mode is supported in the MCTSD02 version.
The command encoding for 16-Mbit devices is represented below :
Function
Device
Deselect
No
Operation
Burst
Stop
Read
Symbol
DESL
CS
1
RAS
X
CAS
X
WE
X
A11
X
A10
X
A[9 :0]
X
NOP
0
1
1
1
X
X
X
BST
0
1
1
0
X
X
X
READ
0
1
0
1
V
0
V
Read with
Auto precharge
Write
READP
0
1
0
1
V
1
V
WRIT
0
1
0
0
V
0
V
Write with
Auto precharge
Bank activate
WRITP
0
1
0
0
V
1
V
ACT
0
0
1
1
V
V
V
Precharge
Selected bank
Precharge
all banks
Mode register set
PRE
0
0
1
0
V
0
X
PALL
0
0
1
0
X
1
X
MRS
0
0
0
0
V
V
V
Refresh
REF
0
0
0
1
X
X
X
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