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參數(shù)資料
| 型號(hào)： | MCTSD01-V100 |
| 廠商： | Lineage Power |
| 英文描述： | SDRAM Controller(同步動(dòng)態(tài)RAM控制器) |
| 中文描述： | SDRAM控制器（同步動(dòng)態(tài)內(nèi)存控制器） |
| 文件頁數(shù)： | 11/12頁 |
| 文件大小： | 417K |
| 代理商： | MCTSD01-V100 |
January 99
SDRAM Controller
MACRO
MCTSD01-V100
Data Sheet
Logic Design Solution
11/12
1.7.3
SDRAM to Microprocessor Timing requirement
1.7.3.1
Microprocessor Read
In Burst mode the SDRAM provides one new data every 10 ns clock period during four clock periods.
The SDRAM_Data_Clock_to_Out equals 6ns to 8ns (see above), which means that the microprocessor should have 2 to
4ns input setup time.
The SDRAM Data_Hold_out equals 3ns, this must be enough for many microprocessor Data_Hold_In timing.
1.7.3.2
Microprocessor Write
In Burst mode the microprocessor should provide one new data every 10 ns clock period during four clock periods. As seen
before, the SDRAM_Data_Setup Timing equals 2 to 3 ns. That is, as for the FPGA, the microprocessor should have a
Clock_to_Out equal to 7 to 8 ns.
1.7.4
Microprocessor to FPGA Timing requirement
The FPGA Clock_to_Out is already described above, it is about 8 ns, which means that the microprocessor should have a
2ns setup time to read FPGA data.
The Lucent Orca Data Sheet provides the following timings :
FPGA SETUP TIME (DELAYED INPUT)
ORCA 2T06A-7
ORCA 2T10A-7
ORCA 2T15A-7
ORCA 2T26A-7
ORCA 2T40A-7
REQUISITE μP CLOCK_TO_OUT TIME
5.6 ns
5.8 ns
5.9 ns
4 ns
4.2 ns
4.4 ns
4.2 ns
4.1 ns
6 ns
5.8 ns
ORCA 3T20A-6
ORCA 3T30A-6
ORCA 3T55A-6
ORCA 3T80A-6
ORCA 3T125A-6
ORCA 3T160A-6
* Fast Clock used
Please refer to the Manufacturer’s Data Sheet for details.
----------- *
----------- *
3.67 to 4.27 ns *
2.31 to 3.21 ns *
----------- *
----------- *
From 5.73 ns to 6.33 ns
From 6.79 ns to 7.69 ns
The FPGA Hold time = 0.
It means that the microprocessor should have, in the worst case, a clock_to_out time equal to (10 – 5.8) = 4.2 ns.
1.7.5
Conclusion
If we consider that the FPGA has a clock_to_out = 8 ns, the following SDRAM devices could be used :
-
Hitachi -10ns (setup=2ns)
-
Micron -8ns (setup=2ns)
-
Siemens -8ns
(setup=2ns)
Not every FPGA densities and family is suitable for a 100 MHz SDRAM Controller.
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