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| 型號(hào)： | MCHC908RK2CSDR2 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 4 MHz, MICROCONTROLLER, PDSO20 |
| 封裝： | PLASTIC, SSOP-20 |
| 文件頁(yè)數(shù)： | 152/181頁(yè) |
| 文件大?。?/td> | 2384K |
| 代理商： | MCHC908RK2CSDR2 |
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Internal Clock Generator Module (ICG)
Data Sheet
MC68HC908RK2 — Rev. 5.0
72
Internal Clock Generator Module (ICG)
MOTOROLA
The amplifier is enabled when the ECGON bit is set and stop mode is not enabled.
When the amplifier is enabled, it will be connected between the OSC1 and OSC2
pins. In its typical configuration, the external oscillator requires five external
components:
1.
Crystal, X1
2.
Fixed capacitor, C1
3.
Tuning capacitor, C2 (can also be a fixed capacitor)
4.
Feedback resistor, R
B
5.
Series resistor, R
S (included in the diagram to follow strict Pierce oscillator
guidelines and may not be required for all ranges of operation, especially
with high frequency crystals). Refer to the crystal manufacturer’s data for
more information.
6.3.3.2 External Clock Input Path
The external clock input path is the means by which the microcontroller uses an
external clock source. The input to the path is the OSC1 pin and the output is the
external clock (ECLK). The path, which contains input buffering, is enabled when
the ECGON bit is set and stop mode is not enabled.
6.3.4 Clock Monitor Circuit
The ICG contains a clock monitor circuit which, when enabled, will continuously
monitor both the external clock (ECLK) and the internal clock (ICLK) to determine
if either clock source has failed based on these conditions:
Either ICLK or ECLK has stopped.
The frequency of IBASE < frequency EREF divided by 4
The frequency of ECLK < frequency of IREF divided by 4
Using the clock monitor requires both clocks to be active (ECGON and ICGON are
both set). To enable the clock monitor, both clocks must also be stable (ECGS and
ICGS both set). This is to prevent the use of the clock monitor when a clock is first
turned on and potentially unstable
NOTE:
Although the clock monitor can be enabled only when the both clocks are stable
(ICGS or ECGS is set), the clock monitor will remain enabled if one of the clocks
goes unstable.
The clock monitor only works if the external slow (EXTSLOW) bit in the
configuration register is properly defined with respect to the external frequency
source.
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