參數(shù)資料
型號: MCF5481CZP166
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 166.66 MHz, RISC PROCESSOR, PBGA388
封裝: 27 X 27 MM, 1 MM PITCH, PLASTIC, MS-034AAL-1, BGA-388
文件頁數(shù): 84/96頁
文件大?。?/td> 2006K
代理商: MCF5481CZP166
MOTOROLA
MCF548x Integrated Microprocessor Hardware Specifications
85
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Document Revision History
Figure 35. PCI Timing
A.11 Fast Ethernet AC Timing Specifications
A.11.1 MII/7-WIRE Interface Timing Specs
The following timing specs meet the requirements for both MII and 7-Wire style interfaces for a range of
transceiver devices. If this interface is to be used with a specific transceiver device the timing specs may be
altered to match that specific transceiver.
P3
Address, Data, and Command (0 -33 Mhz) - Output Valid (tDV)—
11.0
ns
P4
PCI signals (0 - 66 Mhz) - Output Hold (tDH)0
ns
4
P5
PCI signals (0 - 66 Mhz) - Input Hold (tIH)0
ns
5
P6
PCI REQ/GNT (33 < PCI <= 66Mhz) - Output valid (tDV)—
6
ns
6
P7
PCI REQ/GNT (0 < PCI <= 33Mhz) - Output valid (tDV)—
12
ns
P8
PCI REQ/GNT (33 < PCI <= 66Mhz) - Input Setup (tIS)—
5
ns
P9
PCI REQ (0 < PCI <= 33Mhz) - Input Setup (tIS)12
ns
P10
PCI GNT (0 < PCI <= 33Mhz) - Input Setup (tIS)10
ns
1
Please see the PLL chapter for more information on setting the PCI clock rate. Also specific guidelines may need
to be followed when operating the system PLL below certain frequencies.
2
Max cycle rate is determined by CLKIN and how the user has the system PLL configured.
3
All signals defined as PCI bused signals. Does not include PTP (point-to-point) signals.
4
PCI 2.2 spec does not require an output hold time. Although the MCF548X may provide a slight amount of hold, it
is not required or guaranteed.
5
PCI 2.2 spec requires zero input hold.
6
These signals are defined at PTP (Point-to-point) in the PCI 2.2 spec.
Num
Characteristic
Min
Max
Unit
Notes
CLKIN
Input
Setup/Hold
P1
P3
P4
P2
P5
Output Valid
Input Valid
Output
Valid/Hold
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