參數(shù)資料
型號(hào): MCF5481CZP166
廠(chǎng)商: MOTOROLA INC
元件分類(lèi): 微控制器/微處理器
英文描述: 32-BIT, 166.66 MHz, RISC PROCESSOR, PBGA388
封裝: 27 X 27 MM, 1 MM PITCH, PLASTIC, MS-034AAL-1, BGA-388
文件頁(yè)數(shù): 29/96頁(yè)
文件大?。?/td> 2006K
代理商: MCF5481CZP166
MOTOROLA
MCF548x Integrated Microprocessor Hardware Specifications
35
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Signal Description
1.5.1.6.3
AD4—32-bit FlexBus Configuration (FBMODE)
During reset, the FlexBus can be configured to operate in a non-multiplexed 32-bit address with 32-bit data
mode. In this mode, the 32-bit FlexBus AD[31:0] is used for the data bus, and the PCI bus PCIAD[31:0] is
used as the address bus. The FlexBus operating mode is determined by the logic level driven on AD4 at the
rising edge of RSTI. Table 8 shows how the logic level of AD4 corresponds to the FlexBus mode.
1.5.1.6.4
AD3—Byte Enable Configuration (BECONFIG)
The default byte enable mode of the boot FBCS0 is determined by the logic level driven on AD3 at the rising
edge of RSTI. This logic level is reflected as the reset value of CSCR0[BEM]. Table 9 shows how the logic
level of AD3 corresponds to the byte enable mode for FBCS0 at reset.
1.5.1.6.5
AD2—Auto Acknowledge Configuration (AACONFIG)
At reset, the enabling and disabling of auto acknowledge for boot FBCS0 is determined by the logic level
driven on AD2 at the rising edge of RSTI. AACONFIG is multiplexed with AD2 and sampled only at reset.
The AD2 logic level is reflected as the reset value of CSCR0[AA]. Table 10 shows how the AD2 logic level
corresponds to the auto acknowledge timing for FBCS0 at reset. Note that auto acknowledge can be disabled
by driving a logic 0 on AD2 at reset.
Table 7. AD5/FBSIZE Selection of BE/BWE[3:0] Signals
AD5
FlexBus Byte Enable Mode
0BE/BWE[3:0] used as byte/byte write
enables.
1BE/BWE[3:2] configured as TSIZ[1:0].
BE/BWE[1:0] configured as FBADDR[1:0].
Table 8. AD4/FBMODE Selection of Non-Multiplexed 32-bit Address/32-bit Data Mode
AD4
FlexBus Operating Mode
0
PCIAD[31:0] used for PCI bus.
AD[31:0] used for both address and data.
1
AD[31:0] used for data.
PCIAD[31:0] used for address 1
1
If the non-multiplexed 32-bit address/32-bit data mode is selected the PCI bus
cannot be used.
Table 9. AD3/BECONFIG, BE/BWE[3:0] Boot Configuration
AD3
Boot FBCS0 Byte Strobe Configuration
0BE[3:0] can assert for both read and write cycles.
1BWE[3:0] are not asserted for reads;
BWE[3:0] only assert for write cycles
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MCF5481CZP166 32-BIT, 166.66 MHz, RISC PROCESSOR, PBGA388
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