參數(shù)資料
型號: MCF5481CZP166
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 166.66 MHz, RISC PROCESSOR, PBGA388
封裝: 27 X 27 MM, 1 MM PITCH, PLASTIC, MS-034AAL-1, BGA-388
文件頁數(shù): 78/96頁
文件大小: 2006K
代理商: MCF5481CZP166
8
MCF548x Integrated Microprocessor Hardware Specifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MCF548x Family Features
Background debug mode (BDM): Provides low-level debugging in the ColdFire processor
complex. In BDM, the processor complex is halted and a variety of commands can be sent to the
processor to access memory and registers. The external BDM emulator uses a three-pin, serial,
full-duplex channel.
Real-time debug support: BDM requires the processor to be halted, which many real-time
embedded applications cannot permit. Debug interrupts let real-time systems execute a unique
service routine that can quickly save key register and variable contents and return the system to
normal operation without halting. External development systems can access saved data because
the hardware supports concurrent operation of the processor and BDM-initiated commands. In
addition, the option is provided to allow interrupts to occur.
1.4.3
JTAG
The MCF548x family supports circuit board test strategies based on the Test Technology Committee of
IEEE and the Joint Test Action Group (JTAG). The test logic includes a test access port (TAP) consisting of
a 16-state controller, an instruction register, and three test registers (a 1-bit bypass register, a 256-bit
boundary-scan register, and a 32-bit ID register). The boundary scan register links the device’s pins into one
shift register. Test logic, implemented using static logic design, is independent of the device system logic.
The MCF548x implementation can do the following:
Perform boundary scan operations to test circuit board electrical continuity
Sample MCF548x system pins during operation and transparently shift out the result in the
boundary scan register
Bypass the MCF548x for a given circuit board test by effectively reducing the boundary-scan
register to a single bit
Disable the output drive to pins during circuit-board testing
Drive output pins to stable levels
1.4.4
On-Chip Memories
1.4.4.1
Caches
There are two independent caches associated with the ColdFire V4e core complex: a 32-Kbyte instruction
cache and a 32-Kbyte data cache.
Caches improve system performance by providing single-cycle
access to the instruction and data pipelines. This decouples processor performance from system
memory performance, increasing bus availability for on-chip DMA or external devices.
1.4.4.2
System SRAM
The SRAM module provides a general-purpose 32-Kbyte memory block that the ColdFire core can access
in a single cycle. The location of the memory block can be set to any 32-Kbyte address boundary within the
4-Gbyte address space. The memory is ideal for storing critical code or data structures, for use as the system
stack, or for storing FEC data buffers. Because the SRAM module is physically connected to the processor's
high-speed local bus, it can quickly service core-initiated accesses or memory-referencing commands from
the debug module.
The SRAM module is also accessible by multiple non-core bus masters, such as the DMA controller, the
encryption accelerator, and the PCI Controller.
相關(guān)PDF資料
PDF描述
MCF5484CZP200 32-BIT, 200 MHz, RISC PROCESSOR, PBGA388
MCF5485CVR200 32-BIT, 200 MHz, RISC PROCESSOR, PBGA388
MCF5483CVR166 32-BIT, 166.66 MHz, RISC PROCESSOR, PBGA388
MCF5481CZP166 32-BIT, 166.66 MHz, RISC PROCESSOR, PBGA388
MCF5484CVR200 32-BIT, 200 MHz, RISC PROCESSOR, PBGA388
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