參數(shù)資料
型號(hào): MCF5481CZP166
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 166.66 MHz, RISC PROCESSOR, PBGA388
封裝: 27 X 27 MM, 1 MM PITCH, PLASTIC, MS-034AAL-1, BGA-388
文件頁(yè)數(shù): 33/96頁(yè)
文件大?。?/td> 2006K
代理商: MCF5481CZP166
MOTOROLA
MCF548x Integrated Microprocessor Hardware Specifications
39
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Signal Description
In slave mode, the SS signal is a slave select input signal that allows an SPI master to select the DSPI as the
target for transmission.
1.5.1.9.5
DSPI Chip Selects (DSPICS[2:3])
The synchronous peripheral chip selects (DSPICS[2:3]) outputs provide DSPI peripheral chip selects that
can be programmed to be active high or low.
1.5.1.9.6
DSPI Peripheral Chip Select 5/Peripheral Chip Select Strobe
(DSPICS5/PCSS)
DSPICS5 is a peripheral chip select output signal. When the DSPI is in master mode and the
DMCR[PCSSE] bit is cleared, this signal is used to select which slave device the current transfer is intended
for.
PCSS provides a strobe signal that can be used with an external demultiplexer for deglitching of the
DSPICSn signals. When the DSPI is in master mode and DMCR[PCSSE] is set, the PCSS provides the
appropriate timing for the decoding of the DSPICS[0,2,3] signals which prevents glitches from occurring.
This signal is not used in slave mode.
1.5.1.10 FlexCAN Signals
1.5.1.10.1 FlexCAN Transmit (CANTX0, CANTX1)
Controller area network transmit data output.
1.5.1.10.2 FlexCAN Receive (CANRX0, CANRX1)
Controller area network receive data input.
1.5.1.11 I2C I/O SIGNALS
The I2C serial interface module uses the signals in this section.
1.5.1.11.1 Serial Clock (SCL)
This bidirectional open-drain signal is the clock signal for the I2C interface. It is either driven by the I2C
module when the bus is in master mode or it becomes the clock input when the I2C is in slave mode.
1.5.1.11.2 Serial Data (SDA)
This bidirectional open-drain signal is the data input/output for the I2C interface.
1.5.1.12 PSC Module Signals
The PSC modules use the signals in this section. The baud rate clock inputs are not supported.
相關(guān)PDF資料
PDF描述
MCF5484CZP200 32-BIT, 200 MHz, RISC PROCESSOR, PBGA388
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MCF5483CVR166 32-BIT, 166.66 MHz, RISC PROCESSOR, PBGA388
MCF5481CZP166 32-BIT, 166.66 MHz, RISC PROCESSOR, PBGA388
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