參數(shù)資料
型號(hào): MCF5481CZP166
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 166.66 MHz, RISC PROCESSOR, PBGA388
封裝: 27 X 27 MM, 1 MM PITCH, PLASTIC, MS-034AAL-1, BGA-388
文件頁數(shù): 3/96頁
文件大?。?/td> 2006K
代理商: MCF5481CZP166
MOTOROLA
MCF548x Integrated Microprocessor Hardware Specifications
11
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MCF548x Family Features
1.4.6.5
I2C (Inter-Integrated Circuit)
The MCF548x product family provides an I2C two-wire, bidirectional serial bus for on-board
communication.
Multimaster operation with arbitration and collision detection
Calling address recognition and interrupt generation
Automatic switching from master to slave on arbitration loss
Software-selectable acknowledge bit
Start and stop signal generation and detection
Bus busy status detection
1.4.6.6
DMA Serial Peripheral Interface (DSPI)
The DSPI block operates as a basic SPI block with FIFOs providing support for external queue operation.
Data to be transmitted and data received reside in separate FIFOs. The FIFOs can be popped and pushed by
host software or by the system DMA controller. The DSPI supports these SPI features:
Full-duplex, three-wire synchronous transfers
Master and slave mode—two peripheral chip selects in master mode
DMA support
1.4.6.7
Controller Area Network (CAN)
The FlexCAN modules are communication controllers implementing the CAN protocol. The CAN protocol
can be used as an industrial control serial data bus, meeting the specific requirements of real-time processing
and reliable operation in a harsh EMI environment, while maintaining cost-effectiveness. Each of the two
CAN controllers on the MCF548x family products contains sixteen message buffers. The CAN controllers
can be configured to either function as an interface with two separate CAN networks, or as a single 32
message buffer CAN network.
1.4.7
DDR SDRAM Memory Controller
The DDR SDRAM memory controller is a glueless interface to DDR memories. The module uses a 32 bit
memory port and can address a maximum of 1 Gbyte of data with sixteen 64M x 8 (512-Mbit) devices, 4
per chip select. The controller supplies two clock lines and respective inverted clock lines to help minimize
system complexity when using DDR. The module supports either DDR or SDR but not both. This is due to
voltage differences between the memory technologies. The supported memory clock rate is up to 133 MHz.
At this memory clock rate, DDR memory can receive data at an effective rate of up to 266 MHz.
Support for up to 13 lines of row address, 11 lines of column address, 2 lines of bank address, and
up to 4 chip selects
Memory bus width fixed at 32 bits
Four chip selects support up to 1 GByte of SDRAM memory
Support for page mode to maximize the data rate. Page mode remembers active pages for all four
chip selects
Support for sleep mode and self refresh
相關(guān)PDF資料
PDF描述
MCF5484CZP200 32-BIT, 200 MHz, RISC PROCESSOR, PBGA388
MCF5485CVR200 32-BIT, 200 MHz, RISC PROCESSOR, PBGA388
MCF5483CVR166 32-BIT, 166.66 MHz, RISC PROCESSOR, PBGA388
MCF5481CZP166 32-BIT, 166.66 MHz, RISC PROCESSOR, PBGA388
MCF5484CVR200 32-BIT, 200 MHz, RISC PROCESSOR, PBGA388
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