參數(shù)資料
型號: MCF5481CZP166
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 166.66 MHz, RISC PROCESSOR, PBGA388
封裝: 27 X 27 MM, 1 MM PITCH, PLASTIC, MS-034AAL-1, BGA-388
文件頁數(shù): 37/96頁
文件大?。?/td> 2006K
代理商: MCF5481CZP166
42
MCF548x Integrated Microprocessor Hardware Specifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Signal Description
1.5.1.15.5 Development Serial Input/Test Data Input (DSI/TDI)
If MTMOD0 is low, DSI is selected. DSI provides the single-bit communication for debug module
commands.
If MTMOD0 is high, TDI is selected. TDI provides the serial data port for loading the various JTAG
boundary scan, bypass, and instruction registers. Shifting in data depends on the state of the JTAG controller
state machine and the instruction in the instruction register. Shifts occur on the TCK rising edge. TDI has
an internal pull-up resistor, so when not driven low it defaults to high. But if TDI is not used, it should be
tied to EVDD.
1.5.1.15.6 Development Serial Output/Test Data Output (DSO/TDO)
If MTMOD0 is low, DSO is selected. DSO provides single-bit communication for debug module responses.
If MTMOD0 is high, TDO is selected. The TDO output provides the serial data port for outputting data from
JTAG logic. Shifting out data depends on the JTAG controller state machine and the instruction in the
instruction register. Data shifting occurs on the falling edge of TCK. When TDO is not outputting test data,
it is three-stated. TDO can be three-stated to allow bused or parallel connections to other devices having a
JTAG port.
1.5.1.15.7 Test Clock (TCK)
TCK is the dedicated JTAG test logic clock independent of the MCF548x processor clock. Various JTAG
operations occur on the rising or falling edge of TCK. Holding TCK high or low for an indefinite period
does not cause JTAG test logic to lose state information. If TCK is not used, it must be tied to ground.
1.5.1.16 Test Signals
1.5.1.16.1 Test Mode (MTMOD[3:0])
The test mode signals choose between multiplexed debug module and JTAG signals. If MTMOD0 is low,
the part is in normal and background debug mode (BDM); if it is high, it is in normal and JTAG mode. All
other MTMOD values are reserved; MTMOD[3:1] should be tied to ground and MTMOD[3:0] should not
be changed while RSTI is negated
1.5.1.17 Power and Reference Pins
These pins provide system power, ground, and references to the device. Multiple pins are provided for
adequate current capability. All power supply pins must have adequate bypass capacitance for
high-frequency noise suppression.
1.5.1.17.1 Positive Pad Supply (EVDD)
This pin supplies positive power to the I/O pads.
1.5.1.17.2 Positive Core Supply (IVDD)
This pin supplies positive power to the core logic.
相關(guān)PDF資料
PDF描述
MCF5484CZP200 32-BIT, 200 MHz, RISC PROCESSOR, PBGA388
MCF5485CVR200 32-BIT, 200 MHz, RISC PROCESSOR, PBGA388
MCF5483CVR166 32-BIT, 166.66 MHz, RISC PROCESSOR, PBGA388
MCF5481CZP166 32-BIT, 166.66 MHz, RISC PROCESSOR, PBGA388
MCF5484CVR200 32-BIT, 200 MHz, RISC PROCESSOR, PBGA388
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