參數(shù)資料
型號(hào)： MCF5481CZP166
廠商： MOTOROLA INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 32-BIT, 166.66 MHz, RISC PROCESSOR, PBGA388
封裝： 27 X 27 MM, 1 MM PITCH, PLASTIC, MS-034AAL-1, BGA-388
文件頁(yè)數(shù)： 36/96頁(yè)
文件大小： 2006K
代理商： MCF5481CZP166
MOTOROLA
MCF548x Integrated Microprocessor Hardware Specifications
41
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Signal Description
1.5.1.14.2 Timer Outputs (TOUT[3:0])
The programmable timer outputs, TOUTn, pulse or toggle on various timer events.
1.5.1.15 Debug Support Signals
The MCF548x complies with the IEEE 1149.1a JTAG testing standard. JTAG test pins are multiplexed with
background debug pins. Except for TCK, these signals are selected by the value of MTMOD0. If MTMOD0
is high, JTAG signals are chosen; if it is low, debug module signals are chosen. MTMOD0 should be
changed only while RSTI is asserted.
1.5.1.15.1 Processor Clock Output (PSTCLK)
The internal PLL generates this output signal, and is the processor clock output that is used as the timing
reference for the debug bus timing (PSTDDATA[7:0]). PSTCLK is at the same frequency as the core
processor and cache memory. The frequency is 2x the internal system clock.
1.5.1.15.2 Processor Status Debug Data (PSTDDATA[7:0])
Processor status data outputs indicate both processor status and captured address and data values. They
operate at half the processor’s frequency, using PSTCLK. Given that real-time trace information appears as
a sequence of 4-bit data values, there are no alignment restrictions; that is, PST values and operands may
appear on either PSTDDATA[7:0] nibble. The upper nibble, PSTDDATA[7:4], is most significant.
1.5.1.15.3 Development Serial Clock/Test Reset (DSCLK/TRST)
If MTMOD0 is low, DSCLK is selected. DSCLK is the development serial clock for the serial interface to
the debug module. The maximum DSCLK frequency is 1/5 CLKIN.
If MTMOD0 is high, TRST is selected. TRST asynchronously resets the internal JTAG controller to the test
logic reset state, causing the JTAG instruction register to choose the bypass instruction. When this occurs,
JTAG logic is benign and does not interfere with normal MCF548x functionality.
Although TRST is asynchronous, Motorola recommends that it makes an asserted-to-negated transition
only while TMS is held high. TRST has an internal pull-up resistor so if it is not driven low, it defaults to a
logic level of 1. If TRST is not used, it can be tied to ground or, if TCK is clocked, to EVDD. Tying TRST
to ground places the JTAG controller in test logic reset state immediately. Tying it to EVDD causes the JTAG
controller (if TMS is a logic level of 1) to eventually enter test logic reset state after 5 TCK clocks.
1.5.1.15.4 Breakpoint/Test Mode Select (BKPT/TMS)
If MTMOD0 is low, BKPT is selected. BKPT signals a hardware breakpoint to the processor in debug mode.
If MTMOD0 is high, TMS is selected. The TMS input provides information to determine the JTAG test
operation mode. The state of TMS and the internal 16-state JTAG controller state machine at the rising edge
of TCK determine whether the JTAG controller holds its current state or advances to the next state. This
directly controls whether JTAG data or instruction operations occur. TMS has an internal pull-up resistor so
that if it is not driven low, it defaults to a logic level of 1. But if TMS is not used, it should be tied to VDD.
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