參數(shù)資料
型號(hào): MC9RS08KA1CSCR
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 97/136頁(yè)
文件大小: 0K
描述: IC MCU 8-BIT 1K FLASH 8-SOIC
產(chǎn)品培訓(xùn)模塊: Mechatronics
USBSpyder08 Discovery Kit
RS08KA2 Low-End Microcontroller Series
MC9RS08KA8 Microcontroller
標(biāo)準(zhǔn)包裝: 1
系列: RS08
核心處理器: RS08
芯體尺寸: 8-位
速度: 10MHz
外圍設(shè)備: LVD,POR,WDT
輸入/輸出數(shù): 4
程序存儲(chǔ)器容量: 1KB(1K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 63 x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁(yè)面: 726 (CN2011-ZH PDF)
其它名稱: MC9RS08KA1CSCRDKR
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Chapter 8 Central Processor Unit (RS08CPUV1)
MC9RS08KA2 Series Data Sheet, Rev. 4
Freescale Semiconductor
63
8.3.5
Short Addressing Mode (SRT)
SRT addressing mode is capable of addressing only the first 32 bytes in the address map, from $0000 to
$001F. This addressing mode is available for CLR, LDA, and STA instructions. A system can be optimized
by placing the most computation-intensive data in this area of memory.
Because the 5-bit address is embedded in the opcode, only the least significant five bits of the address must
be included in the instruction; this saves program space and execution time. During execution, the CPU
adds nine high-order 0s to the 5-bit operand address and uses the combined 14-bit address ($000x or
$001x) to access the intended operand.
8.3.6
Direct Addressing Mode (DIR)
DIR addressing mode is used to access operands located in direct address space ($0000 through $00FF).
During execution, the CPU adds six high-order 0s to the low byte of the direct address operand that follows
the opcode. The CPU uses the combined 14-bit address ($00xx) to access the intended operand.
8.3.7
Extended Addressing Mode (EXT)
In the extended addressing mode, the 14-bit address of the operand is included in the object code in the
low-order 14 bits of the next two bytes after the opcode. This addressing mode is only used in JSR and
JMP instructions for jump destination address in RS08 MCUs.
8.3.8
Indexed Addressing Mode (IX, Implemented by Pseudo Instructions)
Indexed addressing mode is sometimes called indirect addressing mode because an index register is used
as a reference to access the intended operand.
An important feature of indexed addressing mode is that the operand address is computed during execution
based on the current contents of the X index register located in $000F of the memory map rather than being
a constant address location that was determined during program assembly. This allows writing of a
program that accesses different operand locations depending on the results of earlier program instructions
(rather than accessing a location that was determined when the program was written).
The index addressing mode supported by the RS08 Family uses the register X located at $000F as an index
and D[X] register located at $000E as the indexed data register. By programming the index register X, any
location in the direct page can be read/written via the indexed data register D[X].
These pseudo instructions can be used with all instructions supporting direct, short, and tiny addressing
modes by using the D[X] as the operand.
8.4
Special Operations
Most of what the CPU does is described by the instruction set, but a few special operations must be
considered, such as how the CPU starts at the beginning of an application program after power is first
applied. After the program begins running, the current instruction normally determines what the CPU will
do next. Two exceptional events can cause the CPU to temporarily suspend normal program execution:
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