參數資料
型號： MC9RS08KA1CSCR
廠商： Freescale Semiconductor
文件頁數： 79/136頁
文件大?。?/td> 0K
描述： IC MCU 8-BIT 1K FLASH 8-SOIC
產品培訓模塊： Mechatronics
USBSpyder08 Discovery Kit
RS08KA2 Low-End Microcontroller Series
MC9RS08KA8 Microcontroller
標準包裝： 1
系列： RS08
核心處理器： RS08
芯體尺寸： 8-位
速度： 10MHz
外圍設備： LVD，POR，WDT
輸入/輸出數： 4
程序存儲器容量： 1KB（1K x 8）
程序存儲器類型： 閃存
RAM 容量： 63 x 8
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 5.5 V
振蕩器型： 內部
工作溫度： -40°C ~ 85°C
封裝/外殼： 8-SOIC（0.154"，3.90mm 寬）
包裝： 標準包裝
產品目錄頁面： 726 (CN2011-ZH PDF)
其它名稱： MC9RS08KA1CSCRDKR
Chapter 6 Parallel Input/Output Control
MC9RS08KA2 Series Data Sheet, Rev. 4
Freescale Semiconductor
47
6.3
Pin Control Registers
This section provides information about the registers associated with the parallel I/O ports that are used
for pin control functions.
Refer to tables in Chapter 4, “Memory,” for the absolute address assignments of the pin control registers.
This section refers to registers and control bits only by their names. A Freescale Semiconductor-provided
equate or header file normally is used to translate these names into the appropriate absolute addresses.
6.3.1
Port A Pin Control Registers
The pins associated with port A are controlled by the registers provided in this section. These registers
control the pin pullup/pulldown and slew rate of the port A pins independent of the parallel I/O registers.
6.3.1.1
Internal Pulling Device Enable
An internal pulling device can be enabled for each port pin by setting the corresponding bit in the pulling
device enable register (PTAPEn). The pulling device is disabled if the pin is configured as an output by the
parallel I/O control logic or any shared peripheral output function regardless of the state of the
Table 6-1. PTAD Register Field Descriptions
Field
Description
5:0
PTAD[5:0]
Port A Data Register Bits — For port A pins that are inputs, reads return the logic level on the pin. For port A
pins that are configured as outputs, reads return the last value written to this register. Writes are latched into all
bits of this register. For port A pins that are configured as outputs, the logic level is driven out the corresponding
MCU pin.
Reset forces PTAD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pullup/pulldowns disabled.
76
54
321
0
R
00
00
W
Reset:
000
00
000
Figure 6-3. Port A Data Direction Register (PTADD)
Table 6-2. PTADD Register Field Descriptions
Field
Description
5:4,1:0
PTADD[5:4,1:0]
Data Direction for Port A Bits — These read/write bits control the direction of port A pins and what is read
for PTAD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port A bit n and PTAD reads return the contents of PTADn.
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