參數(shù)資料
型號： MC9RS08KA1CSCR
廠商： Freescale Semiconductor
文件頁數(shù)： 64/136頁
文件大?。?/td> 0K
描述： IC MCU 8-BIT 1K FLASH 8-SOIC
產(chǎn)品培訓(xùn)模塊： Mechatronics
USBSpyder08 Discovery Kit
RS08KA2 Low-End Microcontroller Series
MC9RS08KA8 Microcontroller
標(biāo)準(zhǔn)包裝： 1
系列： RS08
核心處理器： RS08
芯體尺寸： 8-位
速度： 10MHz
外圍設(shè)備： LVD，POR，WDT
輸入/輸出數(shù)： 4
程序存儲器容量： 1KB（1K x 8）
程序存儲器類型： 閃存
RAM 容量： 63 x 8
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 8-SOIC（0.154"，3.90mm 寬）
包裝： 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面： 726 (CN2011-ZH PDF)
其它名稱： MC9RS08KA1CSCRDKR
Chapter 4 Memory
MC9RS08KA2 Series Data Sheet, Rev. 4
Freescale Semiconductor
33
4.7.2
Flash Control Register (FLCR)
4.8
Page Select Register (PAGESEL)
There is a 64-byte window ($00C0–$00FF) in the direct-page reserved for paging access. Programming
the page select register determines the corresponding 64-byte block on the memory map for direct-page
access. For example, when the PAGESEL register is programmed with value $08, the high page registers
($0200–$023F) can be accessed through the paging window ($00C0–$00FF) via direct addressing mode
instructions.
765
432
10
R
0
000
HVEN
MASS
0
PGM1
W
Reset
0
000
0
= Unimplemented or Reserved
Figure 4-4. Flash Control Register (FLCR)
Table 4-3. FLCR Field Descriptions
Field
Description
3
HVEN
High Voltage Enable — This read/write bit enables high voltages to the Flash array for program and erase
operations. HVEN can be set only if either PGM = 1 or MASS = 1 and the proper sequence for program or erase
is followed.
0 High voltage disabled to array.
1 High voltage enabled to array.
2
MASS
Mass Erase Control Bit — This read/write bit configures the memory for mass erase operation.
0 Mass erase operation not selected.
1 Mass erase operation selected.
0
PGM1
1 When Flash security is engaged, writing to PGM bit has no effect. As a result, Flash programming is not allowed.
Program Control Bit — This read/write bit configures the memory for program operation. PGM is interlocked
with the MASS bit such that both bits cannot be equal to 1 or set to 1 at the same time.
0 Program operation not selected.
1 Program operation selected.
765
432
10
R
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
W
Reset
0
000
100
0
Figure 4-5. Page Select Register (PAGESEL)
Table 4-4. PAGESEL Field Descriptions
Field
Description
7:0
AD[13:6]
Page Selector— These bits define the address line bit 6 to bit 13, which determines the 64-byte block boundary
of the memory block accessed via the direct page window. See Figure 4-6 and Table 4-5.
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