參數(shù)資料
型號： MC9RS08KA1CSCR
廠商： Freescale Semiconductor
文件頁數(shù)： 66/136頁
文件大?。?/td> 0K
描述： IC MCU 8-BIT 1K FLASH 8-SOIC
產(chǎn)品培訓(xùn)模塊： Mechatronics
USBSpyder08 Discovery Kit
RS08KA2 Low-End Microcontroller Series
MC9RS08KA8 Microcontroller
標(biāo)準(zhǔn)包裝： 1
系列： RS08
核心處理器： RS08
芯體尺寸： 8-位
速度： 10MHz
外圍設(shè)備： LVD，POR，WDT
輸入/輸出數(shù)： 4
程序存儲器容量： 1KB（1K x 8）
程序存儲器類型： 閃存
RAM 容量： 63 x 8
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 8-SOIC（0.154"，3.90mm 寬）
包裝： 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面： 726 (CN2011-ZH PDF)
其它名稱： MC9RS08KA1CSCRDKR
MC9RS08KA2 Series Data Sheet, Rev. 4
Freescale Semiconductor
35
Chapter 5
Resets, Interrupts, and General System Control
5.1
Introduction
This chapter discusses basic reset and interrupt mechanisms and the various sources of reset and interrupt
in the MC9RS08KA2 Series. Some interrupt sources from peripheral modules are discussed in greater
detail within other chapters of this data sheet. This chapter gathers basic information about all reset and
interrupt sources in one place for easy reference. A few reset and wakeup sources, including the computer
operating properly (COP) watchdog and real-time interrupt (RTI), are not part of on-chip peripheral
systems with their own chapters but are part of the system control logic.
5.2
Features
Reset and interrupt features include:
Multiple sources of reset for flexible system configuration and reliable operation
System reset status register (SRS) to indicate the source of the most recent reset
System interrupt pending register (SIP1) to indicate the status of pending system interrupts
— Analog comparator interrupt with enable
— Keyboard interrupt with enable
— Low-voltage detect interrupt with enable
— Modulo timer interrupt with enable
— Real-time interrupt with enable; available in stop with multiple rates based on a separate 1-kHz
self-clocked source
5.3
MCU Reset
Resetting the MCU provides a way to start processing from a known set of initial conditions. During reset,
most control and status registers are forced to initial values and the program counter is started from
location $3FFD. A JMP instruction (opcode $BC) with operand located at $3FFE–$3FFF must be
programmed into the user application for correct reset operation. The operand defines the location at which
the user program will start. On-chip peripheral modules are disabled and I/O pins are initially configured
as general-purpose high-impedance inputs with pullup/pulldown devices disabled.
The MC9RS08KA2 Series has seven sources for reset:
External pin reset (PIN) — enabled using RSTPE in SOPT
Power-on reset (POR)
Low-voltage detect (LVD)
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