
Analog-to-Digital Converter (ADC10) Module
MC68HC908QL4  MC68HC908QL3  MC68HC908QL2 Data Sheet, Rev. 4
54
Freescale Semiconductor
3.8.2  ADC10 Result High Register (ADRH)
This register holds the MSBs of the result and is updated each time a conversion completes. All other bits 
read as 0s. Reading ADRH prevents the ADC10 from transferring subsequent conversion results into the 
result registers until ADRL is read. If ADRL is not read until the after next conversion is completed, then 
the intermediate conversion result will be lost. In 8-bit mode, this register contains no interlocking with 
ADRL.
3.8.3  ADC10 Result Low Register (ADRL)
This register holds the LSBs of the result. This register is updated each time a conversion completes. 
Reading ADRH prevents the ADC10 from transferring subsequent conversion results into the result 
registers until ADRL is read. If ADRL is not read until the after next conversion is completed, then the 
intermediate conversion result will be lost. In 8-bit mode, there is no interlocking with ADRH.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
0
0
0
0
Write:
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 3-4. ADC10 Data Register High (ADRH), 8-Bit Mode
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
0
0
AD9
AD8
Write:
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 3-5. ADC10 Data Register High (ADRH), 10-Bit Mode
Bit 7
6
5
4
3
2
1
Bit 0
Read:
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
Write:
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 3-6. ADC10 Data Register Low (ADRL)