
Analog-to-Digital Converter (ADC10) Module
MC68HC908QL4  MC68HC908QL3  MC68HC908QL2 Data Sheet, Rev. 4
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Freescale Semiconductor
3.4  Interrupts
When AIEN is set, the ADC10 is capable of generating a CPU interrupt after each conversion. A CPU 
interrupt is generated when the conversion completes (indicated by COCO being set). COCO will set at 
the end of a conversion regardless of the state of AIEN.
3.5  Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
3.5.1  Wait Mode
The ADC10 will continue the conversion process and will generate an interrupt following a conversion if 
AIEN is set. If the ADC10 is not required to bring the MCU out of wait mode, ensure that the ADC10 is not 
in continuous conversion mode by clearing ADCO in the ADC10 status and control register before 
executing the WAIT instruction. In single conversion mode the ADC10 automatically enters a low-power 
state when the conversion is complete. It is not necessary to set the channel select bits (ADCH[4:0]) to 
all 1s to enter a low power state.
3.5.2  Stop Mode
If ACLKEN is clear, executing a STOP instruction will abort the current conversion and place the ADC10 
in a low-power state. Upon return from stop mode, a write to ADCSC is required to resume conversions, 
and the result stored in ADRH and ADRL will represent the last completed conversion until the new 
conversion completes.
If ACLKEN is set, the ADC10 continues normal operation during stop mode. The ADC10 will continue the 
conversion process and will generate an interrupt following a conversion if AIEN is set. If the ADC10 is 
not required to bring the MCU out of stop mode, ensure that the ADC10 is not in continuous conversion 
mode by clearing ADCO in the ADC10 status and control register before executing the STOP instruction. 
In single conversion mode the ADC10 automatically enters a low-power state when the conversion is 
complete. It is not necessary to set the channel select bits (ADCH[4:0]) to all 1s to enter a low-power state.
If ACLKEN is set, a conversion can be initiated while in stop using the external hardware trigger 
ADEXTCO when in external convert mode. The ADC10 will operate in a low-power mode until the trigger 
is asserted, at which point it will perform a conversion and assert the interrupt when complete (if AIEN is 
set).
3.6  ADC10 During Break Interrupts
The system integration module (SIM) controls whether status bits in other modules can be cleared during 
the break state. BCFE in the break flag control register (BFCR) enables software to clear status bits during 
the break state. See BFCR in the SIM section of this data sheet
.
To allow software to clear status bits during a break interrupt, write a 1 to BCFE. If a status bit is cleared 
during the break state, it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a 0 to BCFE. With BCFE cleared (its default state), 
software can read and write registers during the break state without affecting status bits. Some status bits 
have a two-step read/write clearing procedure. If software does the first step on such a bit before the