參數(shù)資料
型號: MC74AC00DT
廠商: ON SEMICONDUCTOR
元件分類: 門電路
英文描述: AC SERIES, QUAD 2-INPUT NAND GATE, PDSO14
封裝: PLASTIC, TSSOP-14
文件頁數(shù): 7/45頁
文件大?。?/td> 434K
代理商: MC74AC00DT
http://onsemi.com
19
10
9
8
7
6
5
4
3
2
1
0
1020304050
0
LOAD CAPACITANCE (pF)
VCC = 5 V
TA = 25°C
t
(ns)
fall
Figure 1–15. tfall versus Capacitance
PCHANNEL MOS
NCHANNEL MOS
OUTPUT
INPUT
-VSS
+ VDD
P - WELL
NSUBSTRATE
N+
P+
N+
P+
Figure 1–16. CMOS Inverter Cross Section with
Latch-up Circuit Schematic
Electrostatic Discharge (ESD) Sensitivity
FACT circuits show excellent resistance to ESD-type
damage. FACT logic is guaranteed to have 2000 V ESD
immunity on all inputs and outputs using Human Body
Model (1500 ohms, 100 pF). FACT parts do not require any
special handling procedures. However, normal handling
precautions should be observed as in the case of any
semi-conductor device.
Figure 1–17 shows the ESD test circuit used in the
sensitivity analysis for this specification. Figure 1–18 is the
pulse waveform required to perform the sensitivity test.
The test procedure is as follows: five pulses, each of
2000 V, are applied to every combination of pins with a five
second cool-down period between each pulse. The polarity is
then reversed and the same procedure, pulse and pin
combination used for an additional five discharges. Continue
until all pins have been tested. The voltage is increased and the
testing procedure is again performed; this entire process is
repeated until failure is detected. This is done to thoroughly
evaluate all pins.
100%
90%
36.8%
10%
VOL
TAGE
AMPLITUDE
tDECAY
TIME
tPEAK
tRISE
tRISE ≤ 15 ns
tDECAY ≤ 350 ns
(R2 + R3) C1 300 ns
Figure 1–17. ESD Pulse Waveform
Figure 1–18. ESD Test Circuit
R1 = 800 k (MIN)
3G (MAX)
R2 = 1500
HIGH VOLTAGE
RELAY
CHARGE
DISCHARGE
CALIBRATE
TEST
DUT
WAVEFORM
TERMINALS
R3 = 1500
C1 = 100 pF
DC
VOLTMETER
REGULATED
HIGH VOLTAGE
SUPPLY
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