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參數(shù)資料
| 型號： | MC74AC00DT |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 門電路 |
| 英文描述： | AC SERIES, QUAD 2-INPUT NAND GATE, PDSO14 |
| 封裝： | PLASTIC, TSSOP-14 |
| 文件頁數(shù)： | 19/45頁 |
| 文件大?。?/td> | 434K |
| 代理商： | MC74AC00DT |
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AC/ACT
VCC
NMOS
Figure 1–33. Interfacing FACT to NMOS, CMOS and
TTL
CMOS OR
TTL
FACT devices can be directly driven by both NMOS and
CMOS families, as shown in Figure 1–33, operating at the
same rail potential without special considerations. This is
possible due to the low input loading of FACT product,
guaranteed to be less than 1
A per input.
Some older technologies, including all existing TTL
families, will not be able to drive FACT circuits directly; this
is due to inadequate high level capability, which is
guaranteed to 2.4 V. There are two simple approaches to the
TTL-to-FACT
interface
problem.
A
TTL-to-CMOS
converter can be constructed employing a resistor pull-up to
VCC of approximately 4.7 k ohms, which is depicted in
Figure 1–34. The correct HIGH level is seen by the CMOS
device while not loading down the TTL driver.
TTL
AC
Figure 1–34. VIH Pull-Up on TTL Outputs
Unfortunately, there will be designs where including a
pull-up resistor will not be acceptable. In these cases, such
as a terminated TTL bus, ON Semiconductor has designed
devices which offer thresholds that are TTL-compatible
(Figure 1–35). These interfaces tend to be slightly slower
than their CMOS-level counterparts due to an extra buffer
stage required for level conversion.
Figure 1–35. TTL Interfacing to ‘ACT
TTL
VCC
ACT
ECL devices cannot directly drive FACT devices.
Interfacing FACT-to-ECL can be accomplished by using
TTL-to-ECL translators and 10125 ECL-to-TTL translators
in addition to following the same rules on the TTL outputs
to CMOS inputs (i.e., a resistor pull-up to VCC of
approximately 4.7 k ohms). The translation can also be
accomplished by a resistive network. A three-resistor
interface between FACT and ECL logic is illustrated in
Figure 1–36a. Figure 1–36b and 1–36c show the translation
from ECL-to-FACT, which is somewhat more complicated.
These two examples offer some possible interfaces between
ECL and FACT logic.
+ 5.0 V
AC/ACT
560
510
470
-5.2 V
Figure 1–36a. Resistive FACT-to-ECL Translation
5.0 V
510
D1
D2
T1
T2
VBB
ECL
510
270
-5.2 V
AC
T1, T2 - 2N2369
D1, D2 - HP5082 - 2811
Figure 1-36b. Single-Ended ECL-to-‘AC Circuit
Figure 1-36c. Differential Output ECL-to-‘AC Circuit
ECL
T1 - 2N2369
D1, D2 - HP5082 - 2811
D3 - 1N414 OR 1N4148
620
D3
AC
D1
D2
620
510
T1
5.0V
- 5.2 V
It should be understood that for FACT, as with other
CMOS technologies, input levels that are between specified
input values will cause both transistors in the CMOS
structure to be conducting. This will cause a low resistive
path from the supply rail to ground, increasing the power
consumption by several orders of magnitude. It is important
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MC74AC00DTR2 | 功能描述:邏輯門 2-6V Quad 2-Input RoHS:否 制造商:Texas Instruments 產品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
| MC74AC00DTR2G | 功能描述:邏輯門 2-6V Quad 2-Input NAND RoHS:否 制造商:Texas Instruments 產品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
| MC74AC00M | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC74AC00MEL | 功能描述:邏輯門 2-6V Quad 2-Input RoHS:否 制造商:Texas Instruments 產品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
| MC74AC00MELG | 功能描述:邏輯門 2-6V Quad 2-Input NAND RoHS:否 制造商:Texas Instruments 產品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
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