參數(shù)資料
型號(hào)： MC74AC00DT
廠(chǎng)商： ON SEMICONDUCTOR
元件分類(lèi)： 門(mén)電路
英文描述： AC SERIES, QUAD 2-INPUT NAND GATE, PDSO14
封裝： PLASTIC, TSSOP-14
文件頁(yè)數(shù)： 28/45頁(yè)
文件大小： 434K
代理商： MC74AC00DT
http://onsemi.com
38
Testing Advanced CMOS Devices with I/O Pins
There are more and more CMOS families becoming
available which can replace TTL circuits. Although testing
these new CMOS units with programs and fixtures which
were developed for bipolar devices will yield acceptable
results most of the time, there are some cases where this
approach will cause the test engineer problems.
Such is the case with parts that have a bidirectional pin,
exemplified by the ’245 Octal Transceiver. If the proper
testing methods are not followed, these types of parts may
not pass those tests for ICC and input leakage currents, even
when there is no fault with the devices.
CMOS circuits, unlike their bipolar counterparts, have
static ICC specification orders of magnitude less than
standard load currents. Most CMOS ICC specifications are
usually less than 100
A. When conducting an ICC test,
greater care must be taken so that other currents will not
mask the actual ICC of the device. These currents are usually
sourced from the inputs and outputs.
Since the static ICC requirements of CMOS devices are so
low, output load currents must be prevented from masking
the current load of the device during an ICC test. Even a
standard 500 ohm load resistor will sink 10 mA at 5 V, which
is more than twice the ICC level being tested. Thus, most
manufacturers will specify that all outputs must be unloaded
during ICC tests.
Another area of concern is identified when considering
the inputs of the device. When the input is in the transition
region, ICC can be several orders of magnitude greater than
the specification. When the input voltage is in the transition
region, both the n-channel and the p-channel transistors in
the input totem-pole structure will be slightly ON, and a
conduction is created from VCC to ground. This conduction
path leads to the increased ICC current seen in the ICC vs. VIN
curve. When the input is at either rail, the input structure no
longer conducts. Most ICC testing is done with all of the
inputs tied to either VCC or ground. If the inputs are allowed
to float, they will typically float to the middle of the
transition region, and the input structure will conduct an
order of magnitude more current than the actual ICC of the
device under test which is being measured by the tester.
10.00
0.00
5.00
VIN (V)
I
(mA)
CC
Figure 1–50. ICC versus IIN
When testing the ICC of a CMOS ’245, problems can arise
depending upon how the test is conducted. Note the structure
of the ’245’s I/O pins illustrated below.
Figure 1–51. ’245 I/O Structure
I/O PAD
DRIVE ENABLE
Each I/O pin is connected to both an input device and an
output device. The pin can be viewed as having three states:
input, output and output disabled. However, only two states
actually exist.
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