參數(shù)資料
型號(hào)： MC74AC00DT
廠商： ON SEMICONDUCTOR
元件分類： 門(mén)電路
英文描述： AC SERIES, QUAD 2-INPUT NAND GATE, PDSO14
封裝： PLASTIC, TSSOP-14
文件頁(yè)數(shù)： 13/45頁(yè)
文件大?。?/td> 434K
代理商： MC74AC00DT
http://onsemi.com
24
‘ACxx Devices
‘ACTxx Devices
VCC
VCC - 0.1 V
70% VCC
30% VCC
0.1 V
0 V
AC TEST
INPUT LEVELS
DC LOW
INPUT RANGE
LOW LEVEL
NOISE
IMMUNITY
DC HIGH
INPUT RANGE
HIGH LEVEL
NOISE
IMMUNITY
TRANSITION
REGION
AC TEST
INPUT LEVELS
DC LOW
INPUT RANGE
LOW LEVEL
NOISE
IMMUNITY
DC HIGH
INPUT RANGE
HIGH LEVEL
NOISE
IMMUNITY
TRANSITION
REGION
VCC
VCC - 0.1 V
0.1 V
0 V
0.8 V
2 V
3 V
Figure 1–22a. Test Input Signal Levels
Figure 1–22b. Test Input Signal Levels
Test Conditions
Figure 1–22a and 1–22b describe the input signal voltage
levels to be used when testing FACT circuits. The AC test
conditions follow industry convention requiring VIN to
range from 0 V for a logic LOW to 3 V for a logic HIGH for
‘ACT devices and 0 V to VCC for ‘AC devices. The DC
parameters are normally tested with VIN at guaranteed input
levels, that is VIH to VIL (see data tables for details). Care
must be taken to adequately decouple these high
performance parts and to protect the test signals from
electrical noise. In an electrically noisy environment, (e.g.,
a tester and handler not specifically designed for high speed
work), DC input levels may need to be adjusted to increase
the noise margin to allow for the extra noise in the tester
which would not be seen in a system.
Noise immunity testing is performed by raising VIN to the
nominal supply voltage of 5 V then dropping to a level
corresponding to VIH characteristics, and then raising again
to the 5 V level. Noise tests can also be performed on the VIL
characteristics by raising VIN from 0 V to VIL, then
returning to 0 V. Both VIH and VIL noise immunity tests
相關(guān)PDF資料
PDF描述
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MC74AC04MR1 AC SERIES, HEX 1-INPUT INVERT GATE, PDSO14
MC74AC05MR2 AC SERIES, HEX 1-INPUT INVERT GATE, PDSO14
MC74ACT05DT ACT SERIES, HEX 1-INPUT INVERT GATE, PDSO14
MC74AC109N AC SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16
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