參數(shù)資料
型號： MC74AC00DT
廠商： ON SEMICONDUCTOR
元件分類： 門電路
英文描述： AC SERIES, QUAD 2-INPUT NAND GATE, PDSO14
封裝： PLASTIC, TSSOP-14
文件頁數(shù)： 24/45頁
文件大小： 434K
代理商： MC74AC00DT
http://onsemi.com
34
Figure 1–42a. High Noise Margin
VCC
30%
GND
VOLTS FROM VCC
VCC = 5.0 V
4
3
2
1
0
0 5 10 15 20 25 30 35 40 45 50
PULSE WIDTH (nS)
SAFE
HAZARD
Figure 1-42b. Low Noise Margin
VCC
70%
GND
VOLTS
3
2
1
0
0 5 10 15 20 25 30 35 40 45 50
PULSE WIDTH (nS)
SAFE
HAZARD
VCC = 5.0V
With over 2 V of noise margins, the FACT family offers
better noise rejection than any other comparable technology.
In any design, the distance that lines run adjacent to each
other should be kept as short as possible. The best situation
is when the lines are perpendicular to each other. For those
situations where lines must run parallel, the effects of
crosstalk can be minimized by line termination. Terminating
a line in its characteristic impedance reduces the amplitude
of an initial crosstalk pulse by 50%. Terminating the line will
also reduce the amount of ringing. Crosstalk problems can
also be reduced by moving lines further apart or by inserting
ground lines or planes between them.
Figure 1–43. Effects of Termination on Crosstalk
SIGNAL ON ACTIVE LINE
PASSIVE LINE
Vn = COUPLED SIGNAL
ZO
A
R
VT
NOISE AMPLITUDE AT A
versus R
V =
R
R + ZO
100%: NO R
67%: R = 2ZO
60%: R = 1.5ZO
50%: R = ZO
~
Ground Bounce
Ground bounce occurs as a result of the intrinsic
characteristics of the leadframes and bondwires of the
packages used to house CMOS devices. As edge rates and
drive capability increase in advanced logic families, the
effects of these intrinsic electrical characteristics become
more pronounced.
Figure 1–44a shows a simple circuit model for a device in
a leadframe driving a standard test load. The inductor L1
represents the parasitic inductance in the ground lead of the
package; inductor L2 represents the parasitic inductance in
the power lead of the package; inductor L3 represents the
parasitic inductance in the output lead of the package; the
resistor R1 represents the output impedance of the device
output, and the capacitor and resistor CL and RL represent
the standard test load on the output of the device.
Figure 1–44a. Output Model
VCC
L2
L3
I
R1
L1
CL
RL
Figure 1-44b. Output Voltage
Figure 1-44c. Output Current
Figure 1-44d. Inductor Voltage
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