參數(shù)資料
型號(hào)： MC74AC00DT
廠商： ON SEMICONDUCTOR
元件分類(lèi)： 門(mén)電路
英文描述： AC SERIES, QUAD 2-INPUT NAND GATE, PDSO14
封裝： PLASTIC, TSSOP-14
文件頁(yè)數(shù)： 6/45頁(yè)
文件大?。?/td> 434K
代理商： MC74AC00DT
http://onsemi.com
18
immune to metastability as possible. This is reflected in the
typical specifications. The true ‘critical’ time where the
input is actually sampled is extremely short: less than 50 ps.
By applying the same reasoning as we did to the
propagation delays to the setup and hold times, it becomes
obvious that the spread from setup to hold time (3 ns
worst-case) really covers devices across the entire process/
temperature/voltage spread. The real difference between the
setup and hold times for any single device, at a specified
temperature and voltage, is negligible.
Capacitive Loading Effects
In addition to temperature and power supply effects,
capacitive loading effects for loads greater than 50 pF should
be taken into account for propagation delays of FACT
devices. Minimum delay numbers may be determined from
the table below. Propagation delays are measured to the 50%
point of the output waveform.
Parameter
Voltage (V)
Unit
Parameter
3
4.5
5.5
Unit
trise
31
22
19
ps/pF
tfall
18
13
12.5
ps/pF
TA = 25°C
The two graphs following, Figures 1–12 and 1–13,
describe propagation delays on FACT devices as affected by
variations in power supply voltage (VCC) and lumped load
capacitance (CL). Figures 1–14 and 1–15 show the effects of
lumped load capacitance on rise and fall times for FACT
devices.
Latch-up
A major problem with CMOS has been its sensitivity to
latch-up, usually attributed to high parasitic gains and high
input impedance. FACT logic is guaranteed not to latch-up
with dynamic currents of 100 mA forced into or out of the
inputs or the outputs under worst case conditions (TA =
125
°C and VCC = 5.5 Vdc). At room temperature the parts
can typically withstand dynamic currents of over 450 mA.
For most designs, latch-up will not be a problem, but the
designer should be aware of its causes and how to prevent it.
DELAY (ns)
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
0
33.5
44.5
55.5
6
VCC (VOLTS)
CL = 1000 pF, tPLH
CL = 1000 pF, tPHL
CL = 470 pF, tPLH
CL = 470 pF, tPHL
CL = 220 pF, tPLH
CL = 220 pF, tPHL
CL = 50 pF, tPLH
CL = 50 pF, tPHL
Figure 1–12. Propagation Delay versus VCC (‘AC00)
22
20
18
16
14
12
10
8
6
4
2
0
100 200 300 400 500 600 700 800 900 1000
DELAY (ns)
LOAD CAPACITANCE (pF)
tPLH
VCC = 4.5 V
tPLH
VCC = 5 V
tPLH
VCC = 5.5 V
tPHL
VCC = 4.5 V
tPHL
VCC = 4.5 V
tPHL
VCC = 5.5 V
Figure 1–13. Propagation Delay versus CL (‘AC00)
FACT devices have been specifically designed to reduce
the possibility of latch-up occurring; ON Semiconductor
accomplished this by lowering the gain of the parasitic
transistors, reducing substrate and p-well resistivity to
increase external drive current required to cause a parasitic
to turn ON, and careful design and layout to minimize the
substrate-injected current coupling to other circuit areas.
10
9
8
7
6
5
4
3
2
1
0
1020304050
0
LOAD CAPACITANCE (pF)
VCC = 5 V
TA = 25°C
t
(ns)
rise
Figure 1–14. trise versus Capacitance
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