參數(shù)資料
型號(hào): MC68SC302
廠商: Motorola, Inc.
英文描述: 32-Bit Microprocessor(32位微處理器)
中文描述: 32位微處理器(32位微處理器)
文件頁(yè)數(shù): 78/218頁(yè)
文件大小: 521K
代理商: MC68SC302
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Communications Processor (CP)
4-32
MC68SC302 USER’S MANUAL
MOTOROLA
erates the TXE interrupt (if enabled). The channel will resume transmission automati-
cally if the RTE bit is set, or after the RESTART TRANSMIT command is given if the
RTE bit is cleared.
Reception Errors:
1. Overrun Error. The HDLC controller maintains an internal three-word FIFO for receiv-
ing data. The CP begins processing the data and updating the CRC when the first
word is received in the FIFO. When a receive FIFO overrun occurs, the channel writes
the received data byte to the internal FIFO over the previously received byte. The pre-
vious data byte and the frame status are lost. Then the channel closes the buffer with
the overrun (OV) bit in the BD set and generates the RXF interrupt (if enabled). The
receiver then enters the hunt mode.
2. Abort Sequence. An abort sequence is detected by the HDLC controller when seven
or more consecutive ones are received while receiving a frame. When this error oc-
curs, the channel closes the buffer by setting the Rx abort sequence (AB) bit in the BD
and generates the RXF interrupt (if enabled). The receiver then enters hunt mode im-
mediately. The CRC and nonoctet error status conditions are not checked on aborted
frames.
3. Nonoctet Aligned Frame. When this error occurs, the channel writes the received data
to the data buffer, closes the buffer, sets the Rx nonoctet aligned frame (NO) bit in the
BD, and generates the RXF interrupt (if enabled). The CRC error status should be dis-
regarded on nonoctet frames. After a nonoctet aligned frame is received, the receiver
enters hunt mode (an immediately following back-to-back frame will be received). The
nonoctet data may be derived from the last word in the data buffer as follows:
Consistent with other HDLC operation, the MSB is the first bit received in this word,
and the low-order valid data bit is the last.
4. CRC Error. When this error occurs, the channel writes the received CRC to the data
buffer, closes the buffer, sets the CR bit in the BD, and generates the RXF interrupt (if
enabled). After receiving a frame with a CRC error, the received enters hunt mode (An
immediately following back-to-back frame will be received). CRC checking cannot be
disabled, but the CRC error may be ignored if checking is not required.
4.5.10.8 HDLC RECEIVE BUFFER DESCRIPTOR (RX BD).
The HDLC controller uses
the Rx BD to report information about the received data for each buffer. The Rx BD is shown
in Figure 4-11.
Figure 4-11. HDLC Receive Buffer Descriptor
MSB
LSB
1
0
0
1
LEADING ZEROS
VALID DATA
NOT VALID DATA
15
E
14
L
13
F
12
NO
11
AB
10
CR
9
8
7
6
5
4
3
2
1
0
OV
-—
DATA LENGTH
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